Acer Aspire 5536 - WISTRON JV50-PU - REV SB, Schematy
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5
4
3
2
1
Project code: 91.4CH01.001
PCB P/N : 48.4C901.001
REVISION :08252- -SB
JV50-PU Block Diagram
PCB STACKUP
DDR2
667/800 MHz
667/800MHz
SYSTEM DC/DC
ISL62392HR
AMD Giffin CPU
S1G2 (35W)
638-Pin uFCPGA638
TOP
46
OUTPUTS
G792
D
D
16,17
INPUTS
35
CRT
VCC
5V_S5(6A)
DDR2
20
DCBATOUT
S
3D3V_S5(6A)
667/800MHz
667/800 MHz
4,5,6,7
LCD
SYSTEM DC/DC
S
GND
16,17
19
TPS51124
47
INPUTS
OUTPUTS
HDMI
21
BOTTOM
1D1V_S0(7.5A)
16X16
DCBATOUT
1D2V_S0(4A)
SYSTEM DC/DC
RT8202
North Bridge
3
M92XT
49
CLK GEN.
ICS9LPRS480BKLFT 71.09480.A03
RTM880N-796-VB-GRT 71.00880.A03
53,54,55,56,57,58,59
INPUTS
OUTPUTS
AMD RS780M
CPU I/F
INTEGRATED GRAHPICS
LVDS, CRT I/F
DCBATOUT
1D8V_S3(11A)
LAN
Giga LAN
TXFM
RJ45
49
RT9025
27
27
26
BCM5764
C
5V_S5
1D1V_M92
C
INT MIC
8,9,10
New card
PWR SW
W83L351YG
RT9161
3D3V_S0
49
30
34
28
A-Link
PCIex1
2D5V_S0
(200mA)
Codec
ALC888
Line In
30
AZALIA
4X4
Mini Card
G957
49
Kedron
a/b/g/n
33
28
3D3V_S0
1D5V_S0
(1A)
Mini Card
MIC In
South Bridge
G9161
49
LPC BUS
30
AMD SB700
USB 2.0/1.1 ports
(10/100/1000Mb)
3D3V_S5
1D2V_S5
(400mA)
INT.SPKR
BIOS
CHARGER
ETHERNET
LPC
50
30
OP AMP
KBC
WPC773
MXIC
MX25L1605
MAX8731
High Definition Audio
APA2057
Winbond
DEBUG
CONN.
29
37
ATA 66/100
INPUTS
OUTPUTS
37
36
B
B
Line Out
(SPDIF)
CHG_PWR
ACPI 1.1
LPC I/F
18V 6.0A
DCBATOUT
UP+5V
5V 100mA
30
Touch
Pad
INT.
KB
PCI/PCI BRIDGE
11,12,13,14,15
38
36
CPU DC/DC
ISL6265HR
45
MODEM
SATA
USB
INPUTS
OUTPUTS
CardReader
Realtek
RTS5159
VCC_CORE_S0_0
0~1.55V 18A
RJ11
MDC Card
MS/MS Pro/xD
/MMC/SD
5 in 1
31
Mini USB
Blue Tooth
32
32
VCC_CORE_S0_1
24
DCBATOUT
HDD SATA
0~1.55V 18A
22
VDDNB
0~1.55V 18A
USB
4 Port
25
ODD SATA
Finger
Printer
23
<Core Design>
<Core Design>
<Core Design>
A
A
31
Camera
Daughter Board
USB Board
Daughter Board
LED Board
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
SB
SB
SB
A3
A3
A3
JV50-PU
JV50-PU
JV50-PU
Date:
Date:
Date:
Friday, December 19, 2008
Friday, December 19, 2008
Friday, December 19, 2008
Sheet
Sheet
Sheet
1
1
1
of
of
of
61
61
61
5
4
3
2
1
5
4
3
2
1
D
D
C
C
B
B
<Core Design>
<Core Design>
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
USB/PCIE Routing
USB/PCIE Routing
USB/PCIE Routing
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
SB
SB
SB
A3
A3
A3
JV50-PU
JV50-PU
JV50-PU
Date:
Date:
Date:
Friday, December 19, 2008
Friday, December 19, 2008
Friday, December 19, 2008
Sheet
Sheet
Sheet
2
2
2
of
of
of
61
61
61
5
4
3
2
1
5
4
3
2
1
3D3V_S0
3D3V_CLK_VDD
3D3V_S0
R215
0R0603-PAD
R221
R221
1
2
3D3V_48MPW R_S0
1
2
C500
C501
DY
DY
C502
C502
C467
C453
C476
C476
C462
C492
C504
Due to PLL issue on current clock chip, the SBlink clock
need to come from SRC clocks for RS740 and RS780.
Future clock chip revision will fix this.
DY
DY
2R3J-GP
2R3J-GP
C511
C511
C506
SC1U10V2KX-1GP
DY
DY
3000mA.80ohm
D
D
Clock chip has internal serial terminations
for differencial pairs, external resistors are
reserved for debug purpose.
3D3V_S0
1
R197
0R0603-PAD
2
1D1V_CLK_VDDIO
C508
SC27P50V2JN-2-GP
1
C508
SC27P50V2JN-2-GP
2008/11/10
R218
R218
DY
DY
1
2
2
C459
C460
C454
C461
C472
C464
C495
3D3V_CLK_VDD
X5
X-14D31818M-35GP
82.30005.891
2ND = 82.30005.B11
10MR2J-L-GP
10MR2J-L-GP
U20
U20
1D1V_CLK_VDDIO
C509
C509
GEN_XTAL_IN
GEN_XTAL_OUT
26
61
VDDATIG
X1
25
62
1
2
VDDATIG_IO
X2
CL=20pF±0.2pF
SC33P50V2JN-3GP
SC33P50V2JN-3GP
48
VDDCPU
CLK_SMBCLK
CLK_SMBDAT
R214
R214
0R2J-2-GP
0R2J-2-GP
47
2
1
2
VDDCPU_IO
SMBCLK
SMBC0_SB
12,16,17
R213
R213
0R2J-2-GP
0R2J-2-GP
3
1
2
SMBDAT
SMBD0_SB
12,16,17
16
VDDSRC
17
VDDSRC_IO
11
30
CLK_PCIE_PEG_1
CLK_PCIE_PEG#_1
R187
R187
1
2
0R2J-2-GP
0R2J-2-GP
VDDSRC_IO
ATIG0T_LPRS
CLK_PCIE_PEG
53
3D3V_CLK_VDD
29
R188
R188
1
2
0R2J-2-GP
0R2J-2-GP
ATIG0C_LPRS
CLK_PCIE_PEG#
53
35
28
CLK_NB_GFX_1
CLK_NB_GFX#_1
R189
R189
1
2
0R2J-2-GP
0R2J-2-GP
VDDSB_SRC
ATIG1T_LPRS
CLK_NB_GFX
9
34
27
R190
R190
1
2
0R2J-2-GP
0R2J-2-GP
VDDSB_SRC_IO
ATIG1C_LPRS
CLK_NB_GFX#
9
1
R238
0R0603-PAD
2
40
VDDSATA
C
4
23
CLKREQ0#
CLKREQ2#
CLKREQ3#
C
TP153 TPAD14-GP
TP153 TPAD14-GP
VDD
CLKREQ0#
C505
SC1U10V2KX-1GP
55
45
CLKREQ1#
CLKREQ# Internal
pull Low
TP160 TPAD14-GP
TP160 TPAD14-GP
VDDHTT
CLKREQ1#
VDD_REF
56
44
TP159 TPAD14-GP
TP159 TPAD14-GP
VDDREF
CLKREQ2#
3D3V_48MPW R_S0
63
39
TP156 TPAD14-GP
TP156 TPAD14-GP
VDD48
CLKREQ3#
CLKREQ4#
38
CLKREQ4#
TP157 TPAD14-GP
TP157 TPAD14-GP
PD#
51
PD#
R191
R191
0R0402-PAD
0R0402-PAD
CLK_PCIE_SB_1
CLK_PCIE_SB#_1
CPU_CLK_1
CPU_CLK#_1
R222
R222
0R0402-PAD
0R0402-PAD
1
2
50
1
2
CPU_CLK
6
11
CLK_PCIE_SB
CPUKG0T_LPRS
SB A-Link
R192
R192
0R0402-PAD
0R0402-PAD
R220
R220
0R0402-PAD
0R0402-PAD
1
2
49
1
2
CPU_CLK#
6
11
CLK_PCIE_SB#
CPUKG0C_LPRS
22
SRC0T_LPRS
R193
R193
0R0402-PAD
0R0402-PAD
CLK_PCIE_LAN_1
CLK_PCIE_LAN#_1
CLK_48
RN65
SRN22-3-GP
1
2
21
64
26
CLK_PCIE_LAN
SRC0C_LPRS
48MHZ_0
CLK48_USB
12
LAN
R194
R194
0R0402-PAD
0R0402-PAD
1
2
20
1
2
4
26
CLK_PCIE_LAN#
SRC1T_LPRS
19
3
SRC1C_LPRS
CLK48_5158E
32
R198
R198
0R0402-PAD
0R0402-PAD
CLK_NB_GPPSB_1
CLK_NB_GPPSB#_1
REF0
1
2
15
59
9
CLK_NB_GPPSB
SRC2T_LPRS
REF0/SEL_HTT66
NB A-Link
R199
R199
0R0402-PAD
0R0402-PAD
REF1
1
2
14
58
9
CLK_NB_GPPSB#
SRC2C_LPRS
REF1/SEL_SATA
REF2
2008/12/09
EC49
EC49
13
57
SRC3T_LPRS
REF2/SEL_27
R200
R200
0R0402-PAD
0R0402-PAD
CLK_PCIE_MINI1_1
CLK_PCIE_MINI1#_1
CLK_PCIE_NEW _1
CLK_PCIE_NEW #_1
EC50
EC50
1
2
12
DY
DY
33
CLK_PCIE_MINI1
SRC3C_LPRS
MINI1
R204
R204
1
0R0402-PAD
0R0402-PAD
2
9
DY
DY
33
CLK_PCIE_MINI1#
SRC4T_LPRS
8
SRC4C_LPRS
R205
R205
1
0R0402-PAD
0R0402-PAD
2
42
43
34
CLK_PCIE_NEW
SRC6T/SATAT_LPRS
GNDSATA
NEW
R206
R206
1
0R0402-PAD
0R0402-PAD
2
41
24
34
CLK_PCIE_NEW #
SRC6C/SATAC_LPRS
GNDATIG
6
7
SRC7T_LPRS/27MHZ_SS
GND
R211
R211
1
0R0402-PAD
0R0402-PAD
2
CLK_PCIE_MINI2_1
CLK_PCIE_MINI2#_1
5
52
33
CLK_PCIE_MINI2
SRC7C_LPRS/27MHZ_NS
GNDHTT
MINI2
2008/11/05
R208
R208
1
0R0402-PAD
0R0402-PAD
2
60
33
CLK_PCIE_MINI2#
GNDREF
46
GNDCPU
R209
R209
1
0R0402-PAD
0R0402-PAD
2
CLK_SRC0T_LPRS
CLK_SRC0C_LPRS
37
1
54
CLK_27M_SSIN
SB_SRC0T_LPRS
GND48
DY
DY
R353
36
SB_SRC0C_LPRS
R353
2
1
32
10
54
CLK_27M_M92
SB_SRC1T_LPRS
GNDSRC
31
18
SB_SRC1C_LPRS
GNDSRC
B
B
2008/11/13
NB CLOCK INPUT TABLE
1KR2F-3-GP
1KR2F-3-GP
33
GNDSB_SRC
R217
R217
0R0402-PAD
0R0402-PAD
CLK_NBHT_CLK_1
CLK_NBHT_CLK#_1
For SB710
NB CLOCKS
RS740
RX780
RS780
1
2
54
9
CLK_NBHT_CLK
HTT0T_LPRS/66M
NB HT
R352
1K2R2F-1-GP
R352
1K2R2F-1-GP
R216
R216
0R0402-PAD
0R0402-PAD
1
2
53
65
9
CLK_NBHT_CLK#
HTT0C_LPRS/66M
GND
DY
DY
HT_REFCLKP
66M SE(SINGLE END)
NC
100M DIFF
100M DIFF
100M DIFF
100M DIFF
ICS9LPRS480BKLFT-GP
ICS9LPRS480BKLFT-GP
HT_REFCLKN
DY
1
DY
REFCLK_P
71.09480.A03
2ND = 71.00880.A03
71.09480.A03
2ND = 71.00880.A03
R229
R229
14M SE (3.3V)
14M SE (1.8V)
14M SE (1.1V)
REF1
110R2F-GP
110R2F-GP
REFCLK_N
NC
NC
vref
2
CLK_SB_25M
11
3D3V_S0
PD#
GFX_REFCLK
GPP_REFCLK
100M DIFF
100M DIFF
100M DIFF(IN/OUT)*
DY
1
DY
RN70
RN70
R234
R234
NC
100M DIFF
8
1
2
3
4
75R2F-2-GP
75R2F-2-GP
2
NC or 100M DIFF OUTPUT
7
3D3V_S5
6
GPPSB_REFCLK
100M DIFF
100M DIFF
100M DIFF
3D3V_S0
5
RUNPW ROK_D
RUNPW ROK_D
42
SRN10KJ-6-GP
SRN10KJ-6-GP
* RS780 can be used as clock buffer to output two PCIE referecence clocks
By deault, chip will configured as input mode, BIOS can program it to output mode.
D
R231
10KR2J-3-GP
DY
D
R230
10KR2J-3-GP
DY
27MHz non-spreading singled clock on pin 5
and 27MHz spread clock on pin 6
R231
10KR2J-3-GP
R230
10KR2J-3-GP
R228
10KR2J-3-GP
SEL_27
REF2
1
R232
150R2F-1-GP
R232
150R2F-1-GP
1
0
*
100MHz differential spreading SRC clock
REF0
REF1
REF0
2
CLK_NB_14M
9
SEL_SATA
REF1
1
100MHz non-spreading differential SATA clock
REF2
2
1
<Core Design>
<Core Design>
<Core Design>
A
A
0
1
0 *
*
100MHz differential spreading SRC clock
R235
75R2F-2-GP
D
R223
10KR2J-3-GP
DY
SEL_HTT66
REF0
66MHz 3.3V single ended HTT clock
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
R225
10KR2J-3-GP
R224
10KR2J-3-GP
R223
10KR2J-3-GP
100MHz differential HTT clock
OSC_14M_NB
CPU_CLK(200MHz)
RS780M
1.1V 158R/90.9R
Title
Title
Title
CLKGEN_ICS9LPRS480
CLKGEN_ICS9LPRS480
CLKGEN_ICS9LPRS480
2008/11/13
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
JV50-PU
JV50-PU
JV50-PU
SB
SB
SB
Date:
Date:
Date:
Friday, December 19, 2008
Friday, December 19, 2008
Friday, December 19, 2008
Sheet
Sheet
Sheet
3
3
3
of
of
of
61
61
61
5
4
3
2
1
5
4
3
2
1
D
D
1D2V_S0
Place close to socket
1.5Amp
C705
C704
C706
C706
C707
C703
C703
C174
C174
C177
C177
DY
DY
DY
DY
DY
DY
DY
DY
ACPU1A
ACPU1A
D1
HT LINK
HT LINK
AE2
VLDT_A0
VLDT_B0
D2
AE3
VLDT_A1
VLDT_B1
D3
AE4
VLDT_A2
VLDT_B2
D4
AE5
VLDT_A3
VLDT_B3
E3
AD1
8
HT_NB_CPU_CAD_H0
L0_CADIN_H0
L0_CADOUT_H0
HT_CPU_NB_CAD_H0
8
E2
AC1
8
HT_NB_CPU_CAD_L0
L0_CADIN_L0
L0_CADOUT_L0
HT_CPU_NB_CAD_L0
8
E1
AC2
8
HT_NB_CPU_CAD_H1
L0_CADIN_H1
L0_CADOUT_H1
HT_CPU_NB_CAD_H1
8
F1
AC3
8
HT_NB_CPU_CAD_L1
L0_CADIN_L1
L0_CADOUT_L1
HT_CPU_NB_CAD_L1
8
G3
AB1
8
HT_NB_CPU_CAD_H2
L0_CADIN_H2
L0_CADOUT_H2
HT_CPU_NB_CAD_H2
8
G2
AA1
8
HT_NB_CPU_CAD_L2
HT_CPU_NB_CAD_L2
8
L0_CADIN_L2
L0_CADOUT_L2
G1
AA2
8
HT_NB_CPU_CAD_H3
HT_CPU_NB_CAD_H3
8
L0_CADIN_H3
L0_CADOUT_H3
C
H1
AA3
C
8
HT_NB_CPU_CAD_L3
HT_CPU_NB_CAD_L3
8
L0_CADIN_L3
L0_CADOUT_L3
J1
W2
8
HT_NB_CPU_CAD_H4
HT_CPU_NB_CAD_H4
8
L0_CADIN_H4
L0_CADOUT_H4
K1
W3
8
HT_NB_CPU_CAD_L4
HT_CPU_NB_CAD_L4
8
L0_CADIN_L4
L0_CADOUT_L4
L3
V1
8
HT_NB_CPU_CAD_H5
HT_CPU_NB_CAD_H5
8
L0_CADIN_H5
L0_CADOUT_H5
L2
U1
8
HT_NB_CPU_CAD_L5
L0_CADIN_L5
L0_CADOUT_L5
HT_CPU_NB_CAD_L5
8
L1
U2
8
HT_NB_CPU_CAD_H6
L0_CADIN_H6
L0_CADOUT_H6
HT_CPU_NB_CAD_H6
8
M1
U3
8
HT_NB_CPU_CAD_L6
L0_CADIN_L6
L0_CADOUT_L6
HT_CPU_NB_CAD_L6
8
N3
T1
8
HT_NB_CPU_CAD_H7
L0_CADIN_H7
L0_CADOUT_H7
HT_CPU_NB_CAD_H7
8
N2
R1
8
HT_NB_CPU_CAD_L7
L0_CADIN_L7
L0_CADOUT_L7
HT_CPU_NB_CAD_L7
8
E5
AD4
8
HT_NB_CPU_CAD_H8
L0_CADIN_H8
L0_CADOUT_H8
HT_CPU_NB_CAD_H8
8
F5
AD3
8
HT_NB_CPU_CAD_L8
L0_CADIN_L8
L0_CADOUT_L8
HT_CPU_NB_CAD_L8
8
F3
AD5
8
HT_NB_CPU_CAD_H9
L0_CADIN_H9
L0_CADOUT_H9
HT_CPU_NB_CAD_H9
8
F4
AC5
8
HT_NB_CPU_CAD_L9
L0_CADIN_L9
L0_CADOUT_L9
HT_CPU_NB_CAD_L9
8
G5
AB4
8
HT_NB_CPU_CAD_H10
L0_CADIN_H10
L0_CADOUT_H10
HT_CPU_NB_CAD_H10
8
H5
AB3
8
HT_NB_CPU_CAD_L10
L0_CADIN_L10
L0_CADOUT_L10
HT_CPU_NB_CAD_L10
8
H3
AB5
8
HT_NB_CPU_CAD_H11
L0_CADIN_H11
L0_CADOUT_H11
HT_CPU_NB_CAD_H11
8
H4
AA5
8
HT_NB_CPU_CAD_L11
L0_CADIN_L11
L0_CADOUT_L11
HT_CPU_NB_CAD_L11
8
K3
Y5
8
HT_NB_CPU_CAD_H12
L0_CADIN_H12
L0_CADOUT_H12
HT_CPU_NB_CAD_H12
8
K4
W5
8
HT_NB_CPU_CAD_L12
L0_CADIN_L12
L0_CADOUT_L12
HT_CPU_NB_CAD_L12
8
L5
V4
8
HT_NB_CPU_CAD_H13
L0_CADIN_H13
L0_CADOUT_H13
HT_CPU_NB_CAD_H13
8
M5
V3
8
HT_NB_CPU_CAD_L13
L0_CADIN_L13
L0_CADOUT_L13
HT_CPU_NB_CAD_L13
8
M3
V5
8
HT_NB_CPU_CAD_H14
L0_CADIN_H14
L0_CADOUT_H14
HT_CPU_NB_CAD_H14
8
M4
U5
8
HT_NB_CPU_CAD_L14
L0_CADIN_L14
L0_CADOUT_L14
HT_CPU_NB_CAD_L14
8
N5
T4
8
HT_NB_CPU_CAD_H15
HT_CPU_NB_CAD_H15
8
L0_CADIN_H15
L0_CADOUT_H15
P5
T3
8
HT_NB_CPU_CAD_L15
HT_CPU_NB_CAD_L15
8
L0_CADIN_L15
L0_CADOUT_L15
J3
Y1
8
HT_NB_CPU_CLK_H0
HT_CPU_NB_CLK_H0
8
L0_CLKIN_H0
L0_CLKOUT_H0
J2
W1
8
HT_NB_CPU_CLK_L0
HT_CPU_NB_CLK_L0
8
L0_CLKIN_L0
L0_CLKOUT_L0
J5
Y4
8
HT_NB_CPU_CLK_H1
HT_CPU_NB_CLK_H1
8
L0_CLKIN_H1
L0_CLKOUT_H1
B
B
K5
Y3
8
HT_NB_CPU_CLK_L1
L0_CLKIN_L1
L0_CLKOUT_L1
HT_CPU_NB_CLK_L1
8
N1
R2
8
HT_NB_CPU_CTL_H0
L0_CTLIN_H0
L0_CTLOUT_H0
HT_CPU_NB_CTL_H0
8
P1
R3
8
HT_NB_CPU_CTL_L0
L0_CTLIN_L0
L0_CTLOUT_L0
HT_CPU_NB_CTL_L0
8
P3
T5
8
HT_NB_CPU_CTL_H1
L0_CTLIN_H1
L0_CTLOUT_H1
HT_CPU_NB_CTL_H1
8
P4
R5
8
HT_NB_CPU_CTL_L1
L0_CTLIN_L1
L0_CTLOUT_L1
HT_CPU_NB_CTL_L1
8
SKT-CPU638P-GP-U2
62.10055.111
2ND = 62.10040.471
3RD = 62.10040.501
SKT-CPU638P-GP-U2
62.10055.111
2ND = 62.10040.471
3RD = 62.10040.501
SKT-BGA638H176
<Core Design>
<Core Design>
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_HT_LINK I/F_(1/4)
CPU_HT_LINK I/F_(1/4)
CPU_HT_LINK I/F_(1/4)
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
JV50-PU
JV50-PU
JV50-PU
SB
SB
SB
Date:
Date:
Date:
Friday, December 19, 2008
Friday, December 19, 2008
Friday, December 19, 2008
Sheet
Sheet
Sheet
4
4
4
of
of
of
61
61
61
5
4
3
2
1
5
4
3
2
1
ACPU1C
ACPU1C
MEM:DATA
MEM:DATA
G12
C11
16
MEM_MA_DATA0
MA_DATA0
MB_DATA0
MEM_MB_DATA0 17
F12
A11
16
MEM_MA_DATA1
MA_DATA1
MB_DATA1
MEM_MB_DATA1 17
H14
A14
16
MEM_MA_DATA2
MA_DATA2
MB_DATA2
MEM_MB_DATA2 17
G14
B14
16
MEM_MA_DATA3
MA_DATA3
MB_DATA3
MEM_MB_DATA3 17
H11
G11
16
MEM_MA_DATA4
MA_DATA4
MB_DATA4
MEM_MB_DATA4 17
H12
E11
16
MEM_MA_DATA5
MA_DATA5
MB_DATA5
MEM_MB_DATA5 17
C13
D12
16
MEM_MA_DATA6
MA_DATA6
MB_DATA6
MEM_MB_DATA6 17
E13
A13
16
MEM_MA_DATA7
MA_DATA7
MB_DATA7
MEM_MB_DATA7 17
Place near to CPU
H15
A15
16
MEM_MA_DATA8
MA_DATA8
MB_DATA8
MEM_MB_DATA8 17
E15
A16
16
MEM_MA_DATA9
MA_DATA9
MB_DATA9
MEM_MB_DATA9 17
4.7u x 4
0.22u X 2
180P x 6
E17
A19
D
D
16
MEM_MA_DATA10
MA_DATA10
MB_DATA10
MEM_MB_DATA10 17
H17
A20
16
MEM_MA_DATA11
MA_DATA11
MB_DATA11
MEM_MB_DATA11 17
E14
C14
16
MEM_MA_DATA12
MEM_MB_DATA12 17
MA_DATA12
MB_DATA12
C262
C262
C736
C736
C737
C263
C258
C258
C254
C254
C249
C255
C250
C256
C251
C252
C252
F14
D14
16
MEM_MA_DATA13
MEM_MB_DATA13 17
MA_DATA13
MB_DATA13
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
C17
C18
16
MEM_MA_DATA14
MEM_MB_DATA14 17
MA_DATA14
MB_DATA14
G17
D18
16
MEM_MA_DATA15
MEM_MB_DATA15 17
MA_DATA15
MB_DATA15
G18
D20
16
MEM_MA_DATA16
MEM_MB_DATA16 17
MA_DATA16
MB_DATA16
C19
A21
16
MEM_MA_DATA17
MEM_MB_DATA17 17
MA_DATA17
MB_DATA17
D22
D24
16
MEM_MA_DATA18
MA_DATA18
MB_DATA18
MEM_MB_DATA18 17
E20
C25
16
MEM_MA_DATA19
MA_DATA19
MB_DATA19
MEM_MB_DATA19 17
E18
B20
16
MEM_MA_DATA20
MA_DATA20
MB_DATA20
MEM_MB_DATA20 17
F18
C20
16
MEM_MA_DATA21
MA_DATA21
MB_DATA21
MEM_MB_DATA21 17
B22
B24
16
MEM_MA_DATA22
MA_DATA22
MB_DATA22
MEM_MB_DATA22 17
C23
C24
16
MEM_MA_DATA23
MA_DATA23
MB_DATA23
MEM_MB_DATA23 17
F20
E23
16
MEM_MA_DATA24
MA_DATA24
MB_DATA24
MEM_MB_DATA24 17
F22
E24
16
MEM_MA_DATA25
MA_DATA25
MB_DATA25
MEM_MB_DATA25 17
H24
G25
16
MEM_MA_DATA26
MA_DATA26
MB_DATA26
MEM_MB_DATA26 17
J19
G26
16
MEM_MA_DATA27
MA_DATA27
MB_DATA27
MEM_MB_DATA27 17
E21
C26
0D9V_S3
16
MEM_MA_DATA28
MA_DATA28
MB_DATA28
MEM_MB_DATA28 17
750 mA
E22
D26
16
MEM_MA_DATA29
MA_DATA29
MB_DATA29
MEM_MB_DATA29 17
CLOSE TO CPU
H20
G23
16
MEM_MA_DATA30
MA_DATA30
MB_DATA30
MEM_MB_DATA30 17
H22
G24
16
MEM_MA_DATA31
MA_DATA31
MB_DATA31
MEM_MB_DATA31 17
Y24
AA24
16
MEM_MA_DATA32
MA_DATA32
MB_DATA32
MEM_MB_DATA32 17
1D8V_S3
ACPU1B
ACPU1B
AB24
AA23
16
MEM_MA_DATA33
MA_DATA33
MB_DATA33
MEM_MB_DATA33 17
AB22
AD24
16
MEM_MA_DATA34
MA_DATA34
MB_DATA34
MEM_MB_DATA34 17
D10
W10
AA21
AE24
VTT1
VTT5
16
MEM_MA_DATA35
MA_DATA35
MB_DATA35
MEM_MB_DATA35 17
C10
MEM:CMD/CTRL/CLK
MEM:CMD/CTRL/CLK
AC10
W22
AA26
VTT2
VTT6
16
MEM_MA_DATA36
MA_DATA36
MB_DATA36
MEM_MB_DATA36 17
B10
AB10
C397
SCD1U10V2KX-4GP
W21
AA25
16
MEM_MA_DATA37
MEM_MB_DATA37 17
VTT3
VTT7
MA_DATA37
MB_DATA37
R381
39D2R2F-L-GP
R381
39D2R2F-L-GP
1
AD10
AA10
Y22
AD26
16
MEM_MA_DATA38
MEM_MB_DATA38 17
VTT4
VTT8
MA_DATA38
MB_DATA38
1D8V_S3
C
A10
AA22
AE25
C
16
MEM_MA_DATA39
MEM_MB_DATA39 17
VTT9
MA_DATA39
MB_DATA39
2
MEMZP
MEMZN
MEM_RSVD_M1
AF10
Y20
AC22
16
MEM_MA_DATA40
MEM_MB_DATA40 17
MEMZP
VREF_DDR_CLAW
MA_DATA40
MB_DATA40
VTT_SENSE
RN48
RN48
1
2
AE10
Y10
1
TP106TPAD14-GP
TP106TPAD14-GP
AA20
AD22
16
MEM_MA_DATA41
MEM_MB_DATA41 17
MEMZN
VTT_SENSE
MA_DATA41
MB_DATA41
R383
39D2R2F-L-GP
1
2
4
AA18
AE20
16
MEM_MA_DATA42
MEM_MB_DATA42 17
MA_DATA42
MB_DATA42
TP111
TP111
1
H16
W17
3
AB18
AF20
RSVD_M1
MEMVREF
16
MEM_MA_DATA43
MA_DATA43
MB_DATA43
MEM_MB_DATA43 17
AB21
AF24
16
MEM_MA_DATA44
MA_DATA44
MB_DATA44
MEM_MB_DATA44 17
MEM_RSVD_M2
TP112
TP112
C391
C388
SRN1KJ-7-GP
SRN1KJ-7-GP
T19
B18
1
AD21
AF23
16,18
MEM_MA0_ODT0
MA0_ODT0
RSVD_M2
16
MEM_MA_DATA45
MA_DATA45
MB_DATA45
MEM_MB_DATA45 17
V22
AD19
AC20
16,18
MEM_MA0_ODT1
MA0_ODT1
16
MEM_MA_DATA46
MA_DATA46
MB_DATA46
MEM_MB_DATA46 17
U21
W26
Y18
AD20
MA1_ODT0
MB0_ODT0
MEM_MB0_ODT0 17,18
16
MEM_MA_DATA47
MA_DATA47
MB_DATA47
MEM_MB_DATA47 17
V19
W23
AD17
AD18
MA1_ODT1
MB0_ODT1
MEM_MB0_ODT1 17,18
16
MEM_MA_DATA48
MA_DATA48
MB_DATA48
MEM_MB_DATA48 17
Y26
W16
AE18
MB1_ODT0
16
MEM_MA_DATA49
MA_DATA49
MB_DATA49
MEM_MB_DATA49 17
T20
W14
AC14
16,18
MEM_MA0_CS#0
MA0_CS_L0
16
MEM_MA_DATA50
MA_DATA50
MB_DATA50
MEM_MB_DATA50 17
U19
V26
Y14
AD14
16,18
MEM_MA0_CS#1
MA0_CS_L1
MB0_CS_L0
MEM_MB0_CS#0 17,18
MEM_MB0_CS#1 17,18
16
MEM_MA_DATA51
MA_DATA51
MB_DATA51
MEM_MB_DATA51 17
U20
W25
Y17
AF19
MA1_CS_L0
MB0_CS_L1
16
MEM_MA_DATA52
MA_DATA52
MB_DATA52
MEM_MB_DATA52 17
V20
U22
AB17
AC18
MA1_CS_L1
MB1_CS_L0
16
MEM_MA_DATA53
MA_DATA53
MB_DATA53
MEM_MB_DATA53 17
AB15
AF16
16
MEM_MA_DATA54
MA_DATA54
MB_DATA54
MEM_MB_DATA54 17
J22
J25
AD15
AF15
16,18
MEM_MA_CKE0
MA_CKE0
MB_CKE0
MEM_MB_CKE0
17,18
16
MEM_MA_DATA55
MA_DATA55
MB_DATA55
MEM_MB_DATA55 17
J20
H26
AB13
AF13
16,18
MEM_MA_CKE1
MA_CKE1
MB_CKE1
MEM_MB_CKE1
17,18
16
MEM_MA_DATA56
MA_DATA56
MB_DATA56
MEM_MB_DATA56 17
AD13
AC12
16
MEM_MA_DATA57
MA_DATA57
MB_DATA57
MEM_MB_DATA57 17
N19
P22
Y12
AB11
MA_CLK_H5
MB_CLK_H5
16
MEM_MA_DATA58
MA_DATA58
MB_DATA58
MEM_MB_DATA58 17
N20
R22
W11
Y11
MA_CLK_L5
MB_CLK_L5
16
MEM_MA_DATA59
MA_DATA59
MB_DATA59
MEM_MB_DATA59 17
E16
A17
AB14
AE14
16
MEM_MA_CLK0_P
MA_CLK_H1
MB_CLK_H1
MEM_MB_CLK0_P
17
16
MEM_MA_DATA60
MA_DATA60
MB_DATA60
MEM_MB_DATA60 17
F16
A18
AA14
AF14
16
MEM_MA_CLK0_N
MA_CLK_L1
MB_CLK_L1
MEM_MB_CLK0_N
17
16
MEM_MA_DATA61
MA_DATA61
MB_DATA61
MEM_MB_DATA61 17
Y16
AF18
AB12
AF11
16
MEM_MA_CLK1_P
MEM_MB_CLK1_P
17
16
MEM_MA_DATA62
MEM_MB_DATA62 17
MA_CLK_H7
MB_CLK_H7
MA_DATA62
MB_DATA62
AA16
AF17
AA12
AD11
16
MEM_MA_CLK1_N
MEM_MB_CLK1_N
17
16
MEM_MA_DATA63
MEM_MB_DATA63 17
MA_CLK_L7
MB_CLK_L7
MA_DATA63
MB_DATA63
P19
R26
MA_CLK_H4
MB_CLK_H4
P20
R25
E12
A12
16
MEM_MA_DM0
MEM_MB_DM0 17
MA_CLK_L4
MB_CLK_L4
MA_DM0
MB_DM0
C15
B16
16
MEM_MA_DM1
MEM_MB_DM1 17
MA_DM1
MB_DM1
N21
P24
E19
A22
16,18
MEM_MA_ADD0
MEM_MB_ADD0
17,18
16
MEM_MA_DM2
MEM_MB_DM2 17
MA_ADD0
MB_ADD0
MA_DM2
MB_DM2
B
B
M20
N24
F24
E25
16,18
MEM_MA_ADD1
MA_ADD1
MB_ADD1
MEM_MB_ADD1
17,18
16
MEM_MA_DM3
MA_DM3
MB_DM3
MEM_MB_DM3 17
N22
P26
AC24
AB26
16,18
MEM_MA_ADD2
MA_ADD2
MB_ADD2
MEM_MB_ADD2
17,18
16
MEM_MA_DM4
MA_DM4
MB_DM4
MEM_MB_DM4 17
M19
N23
Y19
AE22
16,18
MEM_MA_ADD3
MA_ADD3
MB_ADD3
MEM_MB_ADD3
17,18
16
MEM_MA_DM5
MA_DM5
MB_DM5
MEM_MB_DM5 17
M22
N26
AB16
AC16
16,18
MEM_MA_ADD4
MA_ADD4
MB_ADD4
MEM_MB_ADD4
17,18
16
MEM_MA_DM6
MA_DM6
MB_DM6
MEM_MB_DM6 17
L20
L23
Y13
AD12
16,18
MEM_MA_ADD5
MA_ADD5
MB_ADD5
MEM_MB_ADD5
17,18
16
MEM_MA_DM7
MA_DM7
MB_DM7
MEM_MB_DM7 17
M24
N25
16,18
MEM_MA_ADD6
MA_ADD6
MB_ADD6
MEM_MB_ADD6
17,18
L21
L24
G13
C12
16,18
MEM_MA_ADD7
MA_ADD7
MB_ADD7
MEM_MB_ADD7
17,18
16
MEM_MA_DQS0_P
MA_DQS_H0
MB_DQS_H0
MEM_MB_DQS0_P
17
L19
M26
H13
B12
16,18
MEM_MA_ADD8
MA_ADD8
MB_ADD8
MEM_MB_ADD8
17,18
16
MEM_MA_DQS0_N
MA_DQS_L0
MB_DQS_L0
MEM_MB_DQS0_N
17
K22
K26
G16
D16
16,18
MEM_MA_ADD9
MA_ADD9
MB_ADD9
MEM_MB_ADD9
17,18
16
MEM_MA_DQS1_P
MA_DQS_H1
MB_DQS_H1
MEM_MB_DQS1_P
17
R21
T26
G15
C16
16,18
MEM_MA_ADD10
MA_ADD10
MB_ADD10
MEM_MB_ADD10
17,18
16
MEM_MA_DQS1_N
MA_DQS_L1
MB_DQS_L1
MEM_MB_DQS1_N
17
L22
L26
C22
A24
16,18
MEM_MA_ADD11
MA_ADD11
MB_ADD11
MEM_MB_ADD11
17,18
16
MEM_MA_DQS2_P
MA_DQS_H2
MB_DQS_H2
MEM_MB_DQS2_P
17
K20
L25
C21
A23
16,18
MEM_MA_ADD12
MA_ADD12
MB_ADD12
MEM_MB_ADD12
17,18
16
MEM_MA_DQS2_N
MA_DQS_L2
MB_DQS_L2
MEM_MB_DQS2_N
17
V24
W24
G22
F26
16,18
MEM_MA_ADD13
MA_ADD13
MB_ADD13
MEM_MB_ADD13
17,18
16
MEM_MA_DQS3_P
MA_DQS_H3
MB_DQS_H3
MEM_MB_DQS3_P
17
K24
J23
G21
E26
16,18
MEM_MA_ADD14
MA_ADD14
MB_ADD14
MEM_MB_ADD14
17,18
16
MEM_MA_DQS3_N
MA_DQS_L3
MB_DQS_L3
MEM_MB_DQS3_N
17
K19
J24
AD23
AC25
16,18
MEM_MA_ADD15
MA_ADD15
MB_ADD15
MEM_MB_ADD15
17,18
16
MEM_MA_DQS4_P
MA_DQS_H4
MB_DQS_H4
MEM_MB_DQS4_P
17
AC23
AC26
16
MEM_MA_DQS4_N
MA_DQS_L4
MB_DQS_L4
MEM_MB_DQS4_N
17
R20
R24
AB19
AF21
16,18
MEM_MA_BANK0
MA_BANK0
MB_BANK0
MEM_MB_BANK0 17,18
MEM_MB_BANK1 17,18
MEM_MB_BANK2 17,18
MEM_MB_RAS# 17,18
MEM_MB_CAS# 17,18
MEM_MB_W E# 17,18
16
MEM_MA_DQS5_P
MA_DQS_H5
MB_DQS_H5
MEM_MB_DQS5_P
17
R23
U26
AB20
AF22
16,18
MEM_MA_BANK1
MA_BANK1
MB_BANK1
16
MEM_MA_DQS5_N
MA_DQS_L5
MB_DQS_L5
MEM_MB_DQS5_N
17
J21
J26
Y15
AE16
16,18
MEM_MA_BANK2
MA_BANK2
MB_BANK2
16
MEM_MA_DQS6_P
MA_DQS_H6
MB_DQS_H6
MEM_MB_DQS6_P
17
W15
AD16
16
MEM_MA_DQS6_N
MEM_MB_DQS6_N
17
MA_DQS_L6
MB_DQS_L6
R19
U25
W12
AF12
16,18
MEM_MA_RAS#
16
MEM_MA_DQS7_P
MEM_MB_DQS7_P
17
MA_RAS_L
MB_RAS_L
MA_DQS_H7
MB_DQS_H7
T22
U24
W13
AE12
16,18
MEM_MA_CAS#
16
MEM_MA_DQS7_N
MEM_MB_DQS7_N
17
MA_CAS_L
MB_CAS_L
MA_DQS_L7
MB_DQS_L7
T24
U23
16,18
MEM_MA_W E#
MA_WE_L
MB_WE_L
SKT-CPU638P-GP-U2
SKT-CPU638P-GP-U2
SKT-CPU638P-GP-U2
SKT-CPU638P-GP-U2
<Core Design>
<Core Design>
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_DDR_(2/4)
CPU_DDR_(2/4)
CPU_DDR_(2/4)
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
JV50-PU
JV50-PU
JV50-PU
SB
SB
SB
A3
A3
A3
Date:
Date:
Date:
Friday, December 19, 2008
Friday, December 19, 2008
Friday, December 19, 2008
Sheet
Sheet
Sheet
5
5
5
of
of
of
61
61
61
5
4
3
2
1
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