Acer Aspire 1520 1522WLMI - WISTRON EGRET - DISCRETE 135W - REV SC, Schematy
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A
B
C
D
E
EGRET Block Diagram
200-PIN DDR SODIMM
CLK GEN
AMD CPU
ICS
DDR x2
DDR 333/400
Claw Hammer K8
PCB Layer Stackup
ICS950405
8,9,10
L1: Signal 1
L2: GND
L3: Signal 2
L4: Signal 3
L5: VCC
L6: Signal 4
4
4
3
4,5,6,7
TV Encoder
SVIDEO/COMP
VIA VT1623M
TVOUT
HyperTransport
6.4GB/S 16b/8b
17
14
PWR SW
TI
LVDS Transmitter
PCMCIA
SLOT
VIA
LVDS
TPS2224AP
PCI 7420
VIA VT1631
LCD
18
K8N800
27
2* Slot Cardbus
1* 1394
15
Support
TypeII
Battery Charger
46
PCMCIA I/F
AGTL+ CPU I/F + UMA
MAX1645BEEI
Graphic CONN.
27
AGP 8x
11,12,13
RGB CRT
INPUTS
OUTPUTS
CRT
AGP 8X
17
1394
Conn
AD+
BAT+
DCBATOUT
16
25,26
8 bit V-LINK
66MHZ 8x/4x/2x
3
27
SYSTEM DC/DC
43
3
MAX1999
INPUT
OUTPUT
VIA
VT8235CE
ACPI 2.0
5V_S5 ,
3D3V_S5
DCBATOUT
Mini-PCI
SYSTEM DC/DC
PCI Bus / 33MHz
44
USB x
24
802.11a/b/g
AC'97 CODEC
6xUSB 2.0
TPS5110
PCI
VT1612A
Line In
MIC In
INPUT
OUTPUT
30
32
DCBATOUT
2D5V_S3
2D5V_S3
1D5V_S0
AC LINK
31
6-CH
AC97 2.2
PCI GIGA LAN
Realtek
RTL8110SBL
RJ4
29
TXFM
29
Line Out
(SPDIF)
32
1000Mb
MODEM
RJ11
CONN
CPU V_CORE
OP AMP
APA2020
28
41,42
MDC Card
ISL6559CR
29
24
32
INPUT
OUTPUT
LAN PHY
Int. SPKR
32
TXFM
29
10/100Mb
MII
DCBATOUT
VCC_CORE_S0
VIA VT6103L
2
2
29
LPC Bus / 33MHz
LPC I/F
SYSTEM POWER
44,45
FDD6035AL/FDS9412-U
FDS9412-U/SI4892DY/LP2951ACM
ATA 133
19,20,21
APL5508-18VC/APL5308-25AC
INPUT
OUTPUT
Thermal
& Fan
G791
2D5V_S5
5V_S0
3D3V_S3
3D3V_S0
3D3V_LAN_S3
1D8V_S0
+5V_AUX_S5
+5V_UP_S5
2D5V_S0
NS SIO
PC87392
KBC
M38859
FWH
SST-49LF040
5V_S3
3D3V_S5
3D3V_S3
3D3V_S0
DCBATOUT
22
36
33
35
DVD/
CD-R
23
HDD
23
Parallel
port
FIR
Touch
Pad
Int.
KB
TFDU6101E
36
37
34
34
1
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Block Diagram
Size
Document Number
Re v
A3
EGRET
SC
Date:
Friday, July 23, 2004
Sheet
1
of
50
A
B
C
D
E
EGRET REVISION HISTORY
PCI RESOURCE TABLE
DEVICE
IDSEL
PCI IRQ
REQ# / GNT#
P_INTA#
VGA & AGP
AD22
P_INTB#
P_REQ#1/P_GNT#1
PCI7420-CardBus A
AD22
P_INTC#
P_REQ#1/P_GNT#1
PCI7420-CardBus B
PCI7420-IEEE1394A
AD22
P_INTD#
P_REQ#1/P_GNT#1
AD21
P_INTF#
P_REQ#0/P_GNT#0
Mini-PCI
Giga LAN
RTL8110SBL
AD23
P_INTG#
P_REQ#2/P_GNT#2
5,8
VREF_DDR_MEM
VREF_DDR_MEM
4,11,13,39,45
1D2V_HT0A_S0
1D2V_HT0A_S0
1D2V_HT0B_S0
4,6
1D2V_HT0B_S0
5,6,7,9,10,39,45
1D25V_S3
1D25V_S3
12,13,14,15,16,44,50
1D5V_S0
1D5V_S0
6,12,14,15,16,19,20,21,38,39,50
2D5V_S0
2D5V_S0
5,6,7,8,10,38,39,44,45,50
2D5V_S3
2D5V_S3
20,21,39
2D5V_S5
2D5V_S5
3,6,8,11,12,13,14,15,16,17,18,19,20,21,24,25,26,27,28,30,31,32,33,34,35,36,38,41,47,49,50
3D3V_S0
3D3V_S0
18,33,34,38,50
3D3V_S3
3D3V_S3
13,18,19,20,21,22,24,28,29,33,38,43,49,50
3D3V_S5
3D3V_S5
16,17,18,19,20,21,22,23,24,27,30,31,32,33,34,37,38,39,41,42,47,48,49,50
5V_S0
5V_S0
21,38,39,43,44,45,46,48,49
5V_S5
5V_S5
19,21,22,34,38,39,45,46,49
+5V_AUX_S5
+5V_AUX_S5
+5V_UP_S5
18,48,50
+5V_UP_S5
16,18,38,41,43,44,45,46,47,50
DCBATOUT
DCBATOUT
7,41,42
VCC_CORE_S0
VCC_CORE_S0
46,47
AD+
AD+
46,47
DCBATOUT_ISL
BT+
BT+
DCBATOUT_ISL
41,42
24,28,29
3D3V_LAN_S5
3D3V_LAN_S5
25,27
VCC_ASKT_S0
VCC_ASKT_S0
VPP_ASKT_S0
27
VPP_ASKT_S0
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
REVISION HISTORY
Size
Document Number
Re v
A3
EGRET
SC
Date:
Friday, July 23, 2004
Sheet
2
of
50
A
B
C
D
E
6,8,11,12,13,14,15,16,17,18,19,20,21,24,25,26,27,28,30,31,32,33,34,35,36,38,41,47,49,50
3D3V_S0
3D3V_S0
3D3V_S0
3D3V_CLK_S0
L9
BLM21A121S
3D3V_CLK_S0
1
2
C156
C593
SCD1U
C592
SCD1U
C594
SCD1U
C645
SCD1U
C646
SCD1U
FS0~FS2 Have internal Pull-up resistor
FS3 Have internal Pull-down resistor
4
4
C599
SCD1U
C595
SCD1U
C596
SCD1U
C597
SCD1U
C598
SCD1U
U15
SB
PCICLK0
R105
22R3
2
13
1
2
CLK33_CARDBUS 25
VDD
PCI33_0
PCICLK1
PCICLK2
R107
22R3
63.22034.151
9
14
1
2
CLK33_LAN 28
VDD
PCI33_1
R126
22R3
16
17
1
2
CLK33_MINI 30
VDD
PCI33_2
CLK33_LAN Damping only
Stuff for RTL8110SB
19
18
VDD
PCI33_3
PCICLK4
PCICLK5
PCICLK6
PCICLK7
RN13
SRN22-1
29
21
4
5
6
7
8
CLK33_KBC 33
CLK33_SIO 36
CLK33_LPCROM 35
CLK33_SB 21
VDD
PCI33_4
SC
35
22
3
VDD
PCI33_5
38
23
2
VDD
PCI33_6
46
24
1
VDD
PCI33_7
C154
By KDS suggested change
From 78.33034.1B1
To 78.12034.1B1
XI_CLK
CLK33_HT66SEL#0
1
2
43
6
VDDA
HT66_0/PCIHT66SEL0#
CLK33_HT66SEL#1
R101
22R3
Library Issue
Pin32: PD#
7
1
2
PCI33_8_HT66_1/PCIHT66SEL1#
CLK66_NB 12
SC12P
CLK_PD#
PCI33_HT66_2
PCI33_HT66_3
R106
22R3
32
8
1
2
VDDF
PCI33_9_HT66_2
CLK66_VGA 16
X3
XTAL-14D318M-2
R102
22R3
11
1
2
PCI33_11_HT66_3
CLK66_VCLK 21
12
PCI33_10
C155
3
XIN
XO_CLK
CLK66_VGA Damping only
Stuff for K8N800 Discrete
1
2
4
XOUT
44
SRESET#/PD#
SC12P
R108
15R3F
CPUCLK_CY
CLK_24_48SEL#
R127
22R3
1
2
41
28
1
2
6
CPUCLK
CPUT0
24_48MHZ/SEL#
CLK48_CARDBUS 25
37
CPUT1
R112
15R3F
33
R128
10KR3
VSSF
1
2
CPUCLK#_CY
40
6
CPUCLK#
CPUC0
GUICLK Damping only
Stuff for K8N800 UMA
3
3
36
42
CPUC1
VSSA
R86
DY-22R3
ZZ.22034.151
1
2
5
12
GUICLK
VSS
FS0
1
10
FS0/REF0
VSS
R88
22R3
FS1
1
2
48
15
21
APICCLKSB
FS1/REF1
VSS
R109
22R3
FS2
1
2
45
20
20
SIO_OSC
FS2/REF2
VSS
R110
22R3
FS3
1
2
31
27
36
CLK14_SIO
USB/FS3
VSS
30
VSS
25
34
8,21
SMBC_SB
SCLK
VSS
39
VSS
26
47
8,21
SMBD_SB
SDATA
VSS
ICS950405
3D3V_CLK_S0
R85
10KR3
FS0
1
2
R111
22R3
FS3
1
2
19
CLK48_USB
R87
10KR3
FS1
1
2
R114
10KR3
1
2
FS2
Input Configuration
Clock Generator Output
24_48 SEL#
24_48MHz
FS3
0
0
0
0
0
0
0
0
FS2
FS1
FS0
CPU (MHz)
PCI33_HT66 (MHz)
67.27
PCI33 (MHz)
2
0
48MHz
24MHz
2
*
3D3V_CLK_S0
0
0
0
100.90
133.90
168.00
202.00
100.20
133.50
166.70
200.40
33.63
All output Tri-state
1
R113
10KR3
CLK_PD#
001
66.95
33.48
1
2
0
011
0
1
0
67.20
33.60
CLK33_HT66SEL#1
1
2
67.33
66.80
66.75
66.68
66.80
33.67
33.40
33.38
33.34
33.40
R103
10KR3
CLK33_HT66SEL#0
1
2
1
0
R104
10KR3
101
1
1
0
PCIHT66 SEL[1:0]#
SEL1
PCI33_HT66[3:0]
PIN8
1
1
1
Normal Hammer operation
*
SEL0
0
PIN7
PIN11
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
11
00
150.00
180.00
210.00
240.00
270.00
233.33
266.67
300.00
60.00
30.00
30.00
35.00
30.00
33.75
33.33
0
HT66
HT66
PCI33
0
1
60.00
70.00
60.00
0
1
1
HT66
HT66
HT66
*
10
0
PCI33
PCI33
PCI33
1
1
1
1
HT66
PCI33
PCI33
00
67.50
0
1
66.67
66.67
75.00
1
1
1
0
33.33
1
37.50
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CLKGEN_ICS950405
Size
Document Number
Re v
A3
EGRET
SC
Date:
Friday, July 23, 2004
Sheet
3
of
50
A
B
C
D
E
A
B
C
D
E
11,13,39,45
1D2V_HT0A_S0
1D2V_HT0A_S0
1D2V_HT0A_S0
6
1D2V_HT0B_S0
1D2V_HT0B_S0
C105
SCD22U16V3ZY
C107
SCD22U16V3ZY
C106
SCD22U16V3ZY
C109
SCD22U16V3ZY
4
4
HTT for CPU sideA
Transmit power
and NB sideA Receive
power
HTT for CPU sideB
Receive power
and NB sideA
Transmit power
1D2V_HT0A_S0
U11A
1D2V_HT0B_S0
D29
AH29
LAYOUT: Place bypass cap on topside of board near
HTT power pins that are not connected directly to
downstream HTT device, but connected internally to
other HTT power pins.
VLDT0_A
VLDT0_B
D27
AH27
VLDT0_A
VLDT0_B
D25
AG28
VLDT0_A
VLDT0_B
3
C469
SC4D7U10V5ZY
3
C28
AG26
VLDT0_A
VLDT0_B
C26
AF29
VLDT0_A
VLDT0_B
B29
AE28
VLDT0_A
VLDT0_B
B27
AF25
VLDT0_A
VLDT0_B
NB0CADOUT15
CPUCADOUT15
T25
N26
11
NB0CADOUT[15..0]
CPUCADOUT[15..0] 11
L0_CADIN_H15
L0_CADOUT_H15
NB0CADOUTJ15
CPUCADOUTJ15
R25
N27
11
NB0CADOUTJ[15..0]
CPUCADOUTJ[15..0] 11
L0_CADIN_L15
L0_CADOUT_L15
NB0CADOUT14
CPUCADOUT14
CPUCADOUT13
U27
L25
L0_CADIN_H14
L0_CADOUT_H14
NB0CADOUTJ14
CPUCADOUTJ14
U26
M25
L0_CADIN_L14
L0_CADOUT_L14
Used SideB Power Plane
NB0CADOUT13
Used SideA Power Plane
V25
L26
L0_CADIN_H13
L0_CADOUT_H13
NB0CADOUTJ13
CPUCADOUTJ13
U25
L27
L0_CADIN_L13
L0_CADOUT_L13
NB0CADOUT12
CPUCADOUT12
W27
J25
L0_CADIN_H12
L0_CADOUT_H12
NB0CADOUTJ12
CPUCADOUTJ12
W26
K25
L0_CADIN_L12
L0_CADOUT_L12
NB0CADOUT11
CPUCADOUT11
AA27
G25
L0_CADIN_H11
L0_CADOUT_H11
NB0CADOUTJ11
CPUCADOUTJ11
AA26
H25
L0_CADIN_L11
L0_CADOUT_L11
NB0CADOUT10
CPUCADOUT10
AB25
G26
L0_CADIN_H10
L0_CADOUT_H10
NB0CADOUTJ10
CPUCADOUTJ10
AA25
G27
L0_CADIN_L10
L0_CADOUT_L10
NB0CADOUT9
CPUCADOUT9
AC27
E25
L0_CADIN_H9
L0_CADOUT_H9
NB0CADOUTJ9
CPUCADOUTJ9
AC26
F25
L0_CADIN_L9
L0_CADOUT_L9
NB0CADOUT8
CPUCADOUT8
CPUCADOUT7
AD25
E26
L0_CADIN_H8
L0_CADOUT_H8
NB0CADOUTJ8
CPUCADOUTJ8
AC25
E27
L0_CADIN_L8
L0_CADOUT_L8
NB0CADOUT7
T27
N29
L0_CADIN_H7
L0_CADOUT_H7
NB0CADOUTJ7
T28
P29
CPUCADOUTJ7
CPUCADOUTJ6
CPUCADOUTJ5
L0_CADIN_L7
L0_CADOUT_L7
NB0CADOUT6
V29
M28
CPUCADOUT6
CPUCADOUT5
L0_CADIN_H6
L0_CADOUT_H6
NB0CADOUTJ6
U29
M27
L0_CADIN_L6
L0_CADOUT_L6
NB0CADOUT5
V27
L29
L0_CADIN_H5
L0_CADOUT_H5
NB0CADOUTJ5
V28
M29
L0_CADIN_L5
L0_CADOUT_L5
NB0CADOUT4
CPUCADOUT4
Y29
K28
L0_CADIN_H4
L0_CADOUT_H4
NB0CADOUTJ4
CPUCADOUTJ4
W29
K27
L0_CADIN_L4
L0_CADOUT_L4
2
2
NB0CADOUT3
CPUCADOUT3
AB29
H28
L0_CADIN_H3
L0_CADOUT_H3
NB0CADOUTJ3
CPUCADOUTJ3
AA29
H27
L0_CADIN_L3
L0_CADOUT_L3
NB0CADOUT2
CPUCADOUT2
AB27
G29
L0_CADIN_H2
L0_CADOUT_H2
NB0CADOUTJ2
CPUCADOUTJ2
AB28
H29
L0_CADIN_L2
L0_CADOUT_L2
NB0CADOUT1
CPUCADOUT1
AD29
F28
L0_CADIN_H1
L0_CADOUT_H1
NB0CADOUTJ1
CPUCADOUTJ1
AC29
F27
L0_CADIN_L1
L0_CADOUT_L1
NB0CADOUT0
CPUCADOUT0
AD27
E29
L0_CADIN_H0
L0_CADOUT_H0
NB0CADOUTJ0
CPUCADOUTJ0
AD28
F29
L0_CADIN_L0
L0_CADOUT_L0
NB0HTTCLKOUT1
NB0HTTCLKOUT0
CPUHTTCLKOUT1
CPUHTTCLKOUTJ1
Y25
J26
11
NB0HTTCLKOUT1
L0_CLKIN_H1
L0_CLKOUT_H1
CPUHTTCLKOUT1 11
CPUHTTCLKOUTJ1 11
CPUHTTCLKOUT0 11
CPUHTTCLKOUTJ0 11
NB0HTTCLKOUTJ1
NB0HTTCLKOUTJ0
W25
J27
11
NB0HTTCLKOUTJ1
L0_CLKIN_L1
L0_CLKOUT_L1
CPUHTTCLKOUT0
Y27
J29
11
NB0HTTCLKOUT0
L0_CLKIN_H0
L0_CLKOUT_H0
1D2V_HT0B_S0
CPUHTTCLKOUTJ0
Y28
K29
11
NB0HTTCLKOUTJ0
L0_CLKIN_L0
L0_CLKOUT_L0
R289
49D9R3F
CPUHTTCTLIN1
1
2
R27
N25
L0_CTLIN_H1
L0_CTLOUT_H1
R290
49D9R3F
CPUHTTCTLINJ1
NB0HTTCTLOUT
1
2
R26
P25
L0_CTLIN_L1
L0_CTLOUT_L1
CPUHTTCTLOUT0
CPUHTTCTLOUTJ0
T29
P28
11
NB0HTTCTLOUT
L0_CTLIN_H0
L0_CTLOUT_H0
CPUHTTCTLOUT0
11
NB0HTTCTLOUTJ
R29
P27
11
NB0HTTCTLOUTJ
L0_CTLIN_L0
L0_CTLOUT_L0
CPUHTTCTLOUTJ0
11
BGA754-SKT-U
62.10030.041
By ME requset U11 P/N:
Main 62.10030.041
Second 62.10053.191
Third 62.10053.201
1
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CPU(1/4)_HyperTransport I/F
Size
Document Number
Re v
A3
SC
EGRET
Date:
Friday, July 23, 2004
Sheet
4
of
50
A
B
C
D
E
A
B
C
D
E
8
VREF_DDR_MEM
VREF_DDR_MEM
6,7,8,10,38,39,44,45,50
2D5V_S3
2D5V_S3
U11B
1D25V_S3
6,7,9,10,39,45
1D25V_S3
1D25V_S3
TP42
DDRVTT_SENSE
AE13
D17
VTT_SENSE
VTT_A
A18
4
4
VTT_A
B17
C578
SCD1U
C177
SC1000P50V3KX
78.10224.2B1
VTT_A
2D5V_S3
AG12
C17
VREF_DDR_CLAW
MEMVREF1
VTT_A
AF16
VTT_B
R319
34D8R3F-1
MEMZN
MEMZP
1
2
D14
AG16
MEMZN
VTT_B
R318
34D8R3F-1
1
2
C14
AH16
MEMZP
VTT_B
AJ17
VTT_B
VREF_DDR_MEM
AMD suggested change
to 34.8 ohm
For REGISTED DIMM Only
UNBUFFER DIMM NC
MEMRESET#
AG10
MEMRESET_L
M_CKE#0
AE8
M_CKE#0
8,9
MEMCKEA
M_CKE#1
AE7
9
M_DATA[63..0]
M_CKE#1
8,9
MEMCKEB
M_DATA63
A16
MEMDATA63
NOTE: Test with passive probes only.
M_DATA62
M_CLK7
B15
D10
MEMDATA62
MEMCLK_H7
M_CLK7
8,9
M_DATA61
M_CLK#7
M_CLK#6
A12
C10
MEMDATA61
MEMCLK_L7
M_CLK#7
8,9
NOTE: Install to bypass op-amp
M_DATA60
M_CLK6
B11
E12
MEMDATA60
MEMCLK_H6
M_CLK6
8,9
2D5V_S3
M_DATA59
A17
E11
MEMDATA59
MEMCLK_L6
M_CLK#6
8,9
M_DATA58
M_CLK5
A15
AF8
MEMDATA58
MEMCLK_H5
M_CLK5
8,9
M_DATA57
M_CLK#5
C13
AG8
MEMDATA57
MEMCLK_L5
M_CLK#5
8,9
M_DATA56
M_CLK4
2D5V_S3
A11
AF10
MEMDATA56
MEMCLK_H4
M_CLK4
8,9
M_DATA55
M_CLK#4
A10
AE10
MEMDATA55
MEMCLK_L4
M_CLK#4
8,9
C302
SCD1U
M_DATA54
B9
V3
MEMDATA54
MEMCLK_H3
R207
100R3
M_DATA53
M_CLK#1
M_CLK#0
C7
V4
8
1
2
3
4
MEMDATA53
MEMCLK_L3
M_DATA52
A6
K5
7
MEMDATA52
MEMCLK_H2
VREF_DDR_MEM
M_DATA51
M_CLK1
M_CLK0
C11
K4
6
MEMDATA51
MEMCLK_L2
M_CLK1
M_DATA50
A9
R5
5
MEMDATA50
MEMCLK_H1
M_CLK#1
M_CLK#0
M_DATA49
A5
P5
MEMDATA49
MEMCLK_L1
M_DATA48
B5
P3
M_CLK0
RN95
SRN10K-2
MEMDATA48
MEMCLK_H0
M_DATA47
C5
P4
MEMDATA47
MEMCLK_L0
3
C300
SCD1U
C332
SC1000P50V3KX
78.10224.2B1
M_DATA46
3
A4
MEMDATA46
M_DATA45
M_CS#7
M_CS#5
E2
D8
MEMDATA45
MEMCS_L7
R206
100R3
M_DATA44
M_CS#6
M_CS#4
E1
C8
MEMDATA44
MEMCS_L6
M_DATA43
A3
E8
MEMDATA43
MEMCS_L5
M_DATA42
B3
E7
MEMDATA42
MEMCS_L4
M_DATA41
M_CS#3
M_CS#2
M_CS#1
E3
D6
MEMDATA41
MEMCS_L3
M_DATA40
M_DATA38
F1
E6
M_CS#[3..0] 8,9
MEMDATA40
MEMCS_L2
M_DATA39
LAYOUT: Locate close to DIMMs.
G2
C4
MEMDATA39
MEMCS_L1
M_CS#0
G1
E5
MEMDATA38
MEMCS_L0
M_DATA37
L3
MEMDATA37
M_DATA36
M_ARAS#
M_ACAS#
L1
H5
MEMDATA36
MEMRASA_L
M_ARAS#
8,9
M_DATA35
G3
D4
MEMDATA35
MEMCASA_L
M_ACAS#
8,9
M_DATA34
M_AWE#
J2
G5
MEMDATA34
MEMWEA_L
M_AWE#
8,9
M_DATA33
L2
MEMDATA33
M_DATA32
M_ABS#1
M1
K3
MEMDATA32
MEMBANKA1
M_ABS#1
8,9
M_DATA31
M_ABS#0
W1
H3
MEMDATA31
MEMBANKA0
M_ABS#0
8,9
M_DATA30
W3
MEMDATA30
M_DATA29
RSVD_M_AA15
NOTE: Remove to bypass op-amp
AC1
E13
MEMDATA29
NC_E13
M_DATA28
RSVD_M_AA14
AC3
C12
MEMDATA28
NC_C12
M_AA[13..0]
8,9
M_DATA27
M_AA13
W2
E10
MEMDATA27
MEMADDA13
M_DATA26
M_AA12
Y1
AE6
MEMDATA26
MEMADDA12
AMD suggested M_AA13
connect to DIMM pin123
M_DATA25
AC2
AF3
M_AA11
MEMDATA25
MEMADDA11
M_DATA24
AD1
M5
M_AA10
MEMDATA24
MEMADDA10
M_DATA23
AE1
AE5
M_AA9
MEMDATA23
MEMADDA9
M_DATA22
AE3
AB5
M_AA8
MEMDATA22
MEMADDA8
M_DATA21
M_AA7
MEMZN
MEMZP
TP35
AG3
AD3
MEMDATA21
MEMADDA7
M_DATA20
M_AA6
M_AA5
TP34
AJ4
Y5
MEMDATA20
MEMADDA6
M_DATA19
M_DQS8
M_ADM8
TP9
AE2
AB4
MEMDATA19
MEMADDA5
M_DATA18
M_AA4
TP7
AF1
Y3
MEMDATA18
MEMADDA4
2
2
VREF_DDR_CLAW
M_DATA17
M_AA3
AH3
V5
MEMDATA17
MEMADDA3
M_DATA16
M_AA2
AJ3
T5
MEMDATA16
MEMADDA2
M_DATA15
M_DATA14
M_AA1
AJ5
T3
MEMDATA15
MEMADDA1
M_AA0
AJ6
N5
MEMDATA14
MEMADDA0
M_DATA13
AJ7
MEMDATA13
M_DATA12
M_BRAS#
AH9
H4
MEMDATA12
MEMRASB_L
M_BRAS#
8,9
2D5V_S3
M_DATA11
M_BCAS#
M_BWE#
MEMRESET#
TP51
AG5
F5
MEMDATA11
MEMCASB_L
M_BCAS#
8,9
M_DATA10
M_DATA9
M_CS#7
TP48
AH5
F4
MEMDATA10
MEMWEB_L
M_BWE#
8,9
M_CS#6
TP47
AJ9
MEMDATA9
M_DATA8
M_BBS#1
M_CS#5
TP50
AJ10
L5
MEMDATA8
MEMBANKB1
M_BBS#1
8,9
M_DATA7
M_BBS#0
M_CS#4
TP49
AH11
J5
MEMDATA7
MEMBANKB0
M_BBS#0
8,9
C577
SCD1U
M_DATA6
RSVD_M_AA15
TP40
AJ11
MEMDATA6
R328
100R3
M_DATA5
RSVD_M_BA15
RSVD_M_AA14
TP37
AH15
E14
MEMDATA5
NC_E14
VREF_DDR_CLAW
M_DATA4
RSVD_M_BA14
RSVD_M_BA15
TP39
AJ15
D12
MEMDATA4
NC_D12
M_BA[13..0]
8,9
M_DATA3
M_BA13
RSVD_M_BA14
TP38
AG11
E9
MEMDATA3
MEMADDB13
M_DATA2
M_BA12
AJ12
AF6
MEMDATA2
MEMADDB12
M_DATA1
M_BA11
AMD suggested M_BA13
connect to DIMM pin123
AJ14
AF4
MEMDATA1
MEMADDB11
M_DATA0
AJ16
M4
M_BA10
MEMDATA0
MEMADDB10
C579
SCD1U
C580
SC1000P50V3KX
78.10224.2B1
AD5
M_BA9
MEMADDB9
M_ADM8
R1
AC5
M_BA8
9
M_ADM[7..0]
MEMDQS17
MEMADDB8
M_ADM7
A13
AD4
M_BA7
MEMDQS16
MEMADDB7
M_ADM6
M_ADM5
R329
100R3
M_BA6
A7
AA5
MEMDQS15
MEMADDB6
M_BA5
C2
AB3
MEMDQS14
MEMADDB5
M_ADM4
M_BA4
M_BA3
M_BA1
M_BA0
NOT SUPPORT ECC CHECK
AMD suggested remove
PULL-HI resistor.
H1
Y4
MEMDQS13
MEMADDB4
M_ADM3
LAYOUT: Locate close to CPU.
AA1
W5
MEMDQS12
MEMADDB3
M_ADM2
M_BA2
AG1
U5
MEMDQS11
MEMADDB2
M_ADM1
AH7
T4
MEMDQS10
MEMADDB1
M_ADM0
AH13
M3
MEMDQS9
MEMADDB0
M_DQS8
T1
9
M_DQS[7..0]
1
MEMDQS8
1
M_DQS7
CB7
TP53
A14
N3
MEMDQS7
MEMCHECK7
M_DQS6
CB6
TP5
A8
N1
MEMDQS6
MEMCHECK6
M_DQS5
CB5
CB3
TP54
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
D1
U3
MEMDQS5
MEMCHECK5
M_DQS4
CB4
TP11
J1
V1
MEMDQS4
MEMCHECK4
M_DQS3
TP6
TP10
AB1
N2
MEMDQS3
MEMCHECK3
M_DQS2
CB2
TP8
AJ2
P1
MEMDQS2
MEMCHECK2
M_DQS1
CB1
AJ8
U1
MEMDQS1
MEMCHECK1
M_DQS0
CB0
TP12
Title
AJ13
U2
MEMDQS0
MEMCHECK0
CPU(2/4)_DDR
BGA754-SKT-U
Size
Document Number
Re v
A3
EGRET
SC
Date:
Friday, July 23, 2004
Sheet
5
of
50
A
B
C
D
E
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