Acer Aspire 5235 5535 - Wistron Cathedral Peak 2A, Schematy
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5
4
3
2
1
Project code: 91.4K901.001
PCB P/N : 48.4K901.001
REVISION : 08220- -1
Cathedral Peak 2A Block Diagram
PCB STACKUP
DDR2
667/800 MHz
667/800MHz
SYSTEM DC/DC
TPS51125
AMD Giffin CPU
S1G2 (35W)
638-Pin uFCPGA638
37
OUTPUTS
G792
TOP
D
D
8,9
INPUTS
22
VCC
5V_S5(6A)
DDR2
DCBATOUT
S
3D3V_S5(6A)
667/800MHz
667/800 MHz
4,5,6,7
SYSTEM DC/DC
CRT
S
GND
8,9
RT8202 X 2
38
15
INPUTS
OUTPUTS
LCD
BOTTOM
1D1V_S0(7.5A)
16X16
DCBATOUT
14
1D2V_S0(4A)
SYSTEM DC/DC
RT8202
North Bridge
3
39
CLK GEN.
ICS9LPRS480BKLFT 71.09480.A03
RTM880N-796-VB-GRT 71.00880.A03
INPUTS
OUTPUTS
AMD RS780M
CPU I/F
INTEGRATED GRAHPICS
LVDS, CRT I/F
DCBATOUT
1D8V_S3(11A)
LAN
Giga LAN
TXFM
RJ45
RT9026PFP
39
27
27
26
BCM5764
DDR_VREF_S3
C
5V_S5
C
11,12,13
0D9V_S3
New card
PWR SW
TPS2231
40
RT9161
3D3V_S0
INT MIC
28
28
A-Link
PCIex1
2D5V_S0
(200mA)
30
Codec
ALC268
AZALI
A
4X4
Mini Card
G957
40
Kedron
a/b/g/n
28
MIC In
29
3D3V_S0
1D5V_S0
(1A)
South Bridge
30
G9161
40
LPC BUS
AMD SB700
USB 2.0/1.1 ports
(10/100/1000Mb)
1D2V_S5
(400mA)
3D3V_S5
INT.SPKR
CHARGER
BIOS
ETHERNET
LPC
MAX8731
41
30
OP AMP
KBC
WPC773L
MXIC
MX25L1605
High Definition Audio
APA2057
Winbond
DEBUG
CONN.
30
32
ATA 66/100
INPUTS
OUTPUTS
32
31
B
B
Line Out
(No-SPDIF)
CHG_PWR
ACPI 1.1
LPC I/F
18V 6.0A
DCBATOUT
UP+5V
5V 100mA
30
Touch
Pad
INT.
KB
PCI/PCI BRIDGE
17,18,19,20,21
31
31
CPU DC/DC
ISL6265HR
36
MODEM
SATA
USB
INPUTS
OUTPUTS
CardReader
Realtek
RTS5158E
RJ11
MDC Card
MS/MS Pro/xD
/MMC/SD
5 in 1
VCC_CORE_S0_0
0~1.55V 18A
24
Mini USB
Blue Tooth
25
25
VCC_CORE_S0_1
24
DCBATOUT
HDD SATA
0~1.55V 18A
23
VDDNB
0~1.55V 18A
USB
3 Port
24
ODD SATA
23
<Core Design>
<Core Design>
<Core Design>
A
A
Camera
Daughter Board
LAUNCH Board
16
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
08575
Title
Title
Title
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
-1
-1
-1
A3
A3
A3
Cathedral Peak 2A
Cathedral Peak 2A
Cathedral Peak 2A
Date:
Date:
Date:
Friday, August 22, 2008
Friday, August 22, 2008
Friday, August 22, 2008
Sheet
Sheet
Sheet
1
1
1
of
of
of
43
43
43
5
4
3
2
1
5
4
3
2
1
D
D
C
C
B
B
<Core Design>
<Core Design>
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
HISTORY
HISTORY
HISTORY
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
Cathedral Peak 2A
Cathedral Peak 2A
Cathedral Peak 2A
-1
-1
-1
Date:
Date:
Date:
Friday, August 22, 2008
Friday, August 22, 2008
Friday, August 22, 2008
Sheet
Sheet
Sheet
2
2
2
of
of
of
43
43
43
5
4
3
2
1
5
4
3
2
1
3D3V_S0
3D3V_CLK_VDD
3D3V_S0
R
140
0R0603-PAD
R139
R139
1
2
3D3V_48MPWR_S0
1
2
C
213
C2
20
DY
D
Y
C217
C217
C219
C216
C209
C209
C193
C194
C211
Due to PLL issue on current clock chip, the SBlink clock
need to come from SRC clocks for RS740 and RS780.
Future clock chip revision will fix this.
DY
DY
2R3J-GP
2R3J-GP
C190
C190
C197
SC1U10V2KX-1GP
DY
DY
3000mA.80ohm
D
D
Clock chip has internal serial terminations
for differencial pairs, external resistors are
reserved for debug purpose.
3D3V_S0
SB
R308
0R0603-PAD
1
2
1D1V_S0
1D1V_CLK_VDDIO
C201
SC27P50V2JN-2-GP
R154
0R3-0-U-GP
R154
0R3-0-U-GP
DY
DY
R141
R141
1
2
DY
DY
1
2
1
2
C2
30
C
232
C192
C215
C200
C210
C218
3D3V_CLK_VDD
X4
X-14D31818M-35GP
82.30005.891
2ND = 82.30005.951
10MR2J-L-GP
10MR2J-L-GP
U13
U13
1D1V_CLK_VDDIO
C198
C198
GEN_XTAL_IN
GEN_XTAL_OUT
26
61
VDDATIG
X1
25
62
1
2
VDDATIG_IO
X2
CL=20pF±0.2pF
G45
G45
SC33P50V2JN-3GP
SC33P50V2JN-3GP
48
VDDCPU
CLK_SMBCLK
CLK_SMBDAT
G44
G44
47
2
2
1
SMBC0_SB
8,9,18
VDDCPU_IO
SMBCLK
3
2
1
SMBDAT
SMBD0_SB
8,9,18
GAP-CLOSE
GAP-CLOSE
16
VDDSRC
GAP-CLOSE
GAP-CLOSE
17
VDDSRC_IO
11
30
SB
VDDSRC_IO
ATIG0T_LPRS
TP207 TPAD14-GP
TP207 TPAD14-GP
3D3V_CLK_VDD
29
ATIG0C_LPRS
TP208 TPAD14-GP
TP208 TPAD14-GP
35
28
CLKREQ# Internal
pull Low
VDDSB_SRC
ATIG1T_LPRS
CLK_NB_GFX
12
34
27
VDDSB_SRC_IO
ATIG1C_LPRS
CLK_NB_GFX#
12
1
R295
0R0603-PAD
2
40
VDDSATA
C
CLKREQ0#
CLKREQ2#
CLKREQ3#
C
4
23
TP128 TPAD14-GP
TP128 TPAD14-GP
VDD
CLKREQ0#
C206
SC1U10V2KX-1GP
CLKREQ1#
55
45
TP135 TPAD14-GP
TP135 TPAD14-GP
VDDHTT
CLKREQ1#
VDD_REF
56
44
TP132 TPAD14-GP
TP132 TPAD14-GP
VDDREF
CLKREQ2#
3D3V_48MPWR_S0
63
39
TP136 TPAD14-GP
TP136 TPAD14-GP
VDD48
CLKREQ3#
CLKREQ4#
38
TP133 TPAD14-GP
TP133 TPAD14-GP
CLKREQ4#
PD#
51
PD#
R365
R365
0R0402-P
AD
0R0402-PAD
CLK_PCIE_SB_1
CLK_PCIE_SB#_1
CPU_CLK_1
CPU_CLK#_1
R377
R377
0R0402-P
AD
0R0402-PAD
1
2
50
1
2
CPU_CLK
6
17
CLK_PCIE_SB
CPUKG0T_LPRS
SB A-Link
R366
R366
0R0402-P
AD
0R0402-PAD
R378
R378
0R0402-P
AD
0R0402-PAD
1
2
49
1
2
CPU_CLK#
6
17
CLK_PCIE_SB#
CPUKG0C_LPRS
22
SRC0T_LPRS
R367
R367
0R0402-P
AD
0R0402-PAD
CLK_PCIE_LAN_1
CLK_PCIE_LAN#_1
CLK_48
1
2
21
64
RN22
RN22
26
CLK_PCIE_LAN
SRC0C_LPRS
48MHZ_0
CLK48_USB
18
LAN
R368
R368
0R0402-P
AD
0R0402-PAD
1
2
20
1
2
4
26
CLK_PCIE_LAN#
SRC1T_LPRS
19
3
SRC1C_LPRS
CLK48_5158E
25
R369
R369
0R0402-P
AD
0R0402-PAD
CLK_NB_GPPSB_1
CLK_NB_GPPSB#_1
REF0
1
2
15
59
12
CLK_NB_GPPSB
SRC2T_LPRS
REF0/SEL_HTT66
NB A-Link
R370
R370
0R0402-P
AD
0R0402-PAD
REF1
1
2
14
58
SRN33J-5-GP-U
SRN33J-5-GP-U
12
CLK_NB_GPPSB#
SRC2C_LPRS
REF1/SEL_SATA
REF2
EC68
EC68
SA
13
57
SRC3T_LPRS
REF2/SEL_27
R371
R371
0R0402-P
AD
0R0402-PAD
CLK_PCIE_MINI1_1
CLK_PCIE_MINI1#_1
CLK_PCIE_NEW_1
CLK_PCIE_NEW#_1
EC69
EC69
DY
DY
1
2
12
28
CLK_PCIE_MINI1
SRC3C_LPRS
MINI
R372
R372
0R0402-P
AD
0R0402-PAD
DY
DY
1
2
9
28
CLK_PCIE_MINI1#
SRC4T_LPRS
8
SRC4C_LPRS
R373
R373
0R0402-P
AD
0R0402-PAD
1
2
42
43
28
CLK_PCIE_NEW
SRC6T/SATAT_LPRS
GNDSATA
NEW
R374
R374
0R0402-P
AD
0R0402-PAD
1
2
41
24
28
CLK_PCIE_NEW#
SRC6C/SATAC_LPRS
GNDATIG
CLK_SRC0T_LPRS
CLK_SRC0C_LPRS
6
7
TP201
TPAD14-GTP201
TPAD14-GP
SRC7T_LPRS/27MHZ_SS
GND
5
52
TP202
TPAD14-GTP202
TPAD14-GP
SRC7C_LPRS/27MHZ_NS
GNDHTT
60
GNDREF
46
GNDCPU
37
1
SB_SRC0T_LPRS
GND48
36
SB_SRC0C_LPRS
32
10
SB_SRC1T_LPRS
GNDSRC
31
18
SB_SRC1C_LPRS
GNDSRC
B
B
NB CLOCK INPUT TABLE
33
GNDSB_SRC
R375
R375
0R0402-P
AD
0R0402-PAD
CLK_NBHT_CLK_1
CLK_NBHT_CLK#_1
NB CLOCKS
RS740
RX780
RS780
1
2
54
12
CLK_NBHT_CLK
HTT0T_LPRS/66M
NB HT
R376
R376
0R0402-P
AD
0R0402-PAD
1
2
53
65
12
CLK_NBHT_CLK#
HTT0C_LPRS/66M
GND
HT_REFCLKP
66M SE(SINGLE END)
NC
100M DIFF
100M DIFF
100M DIFF
100M DIFF
ICS9LPRS480BKLFT-GP
71.09480.A03
2nd = 71.00880.A03
ICS9LPRS480BKLFT-GP
71.09480.A03
2nd = 71.00880.A03
HT_REFCLKN
REFCLK_P
14M SE (3.3V)
14M SE (1.8V)
14M SE (1.1V)
REFCLK_N
NC
NC
vref
3D3V_S0
PD#
GFX_REFCLK
GPP_REFCLK
100M DIFF
100M DIFF
100M DIFF(IN/OUT)*
RN29
RN29
NC
100M DIFF
NC or 100M DIFF OUTPUT
8
1
2
3
4
PCI_REQ#5
RUNPWROK_D
7
PCI_REQ#5
17
3D3V_S5
GPPSB_REFCLK
100M DIFF
100M DIFF
100M DIFF
6
3D3V_S0
5
RUNPWROK_D
34
SRN10KJ-6-GP
SRN10KJ-6-GP
* RS780 can be used as clock buffer to output two PCIE referecence clocks
By deault, chip will configured as input mode, BIOS can program it to output mode.
D
R144
10KR2J-3-GP
DY
D
R148
10KR2J-3-GP
DY
D
R151
10KR2J-3-GP
DY
27MHz non-spreading singled clock on pin 5
and 27MHz spread clock on pin 6
R144
10KR2J-3-GP
R148
10KR2J-3-GP
R151
10KR2J-3-GP
SEL_27
REF2
1
R145
150R2F-1-GP
0
*
100MHz differential spreading SRC clock
REF0
REF1
REF0
2
1
CLK_NB_14M
12
SEL_SATA
REF1
1
100MHz non-spreading differential SATA clock
REF2
2
1
<Core Design>
<Core Design>
<Core Design>
A
A
0
1
0 *
*
100MHz differential spreading SRC clock
R149
75R2F-2-GP
D
R146
10KR2J-3-GP
DY
D
R147
10KR2J-3-GP
DY
D
R150
10KR2J-3-GP
DY
SEL_HTT66
REF0
66MHz 3.3V single ended HTT clock
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
R146
10KR2J-3-GP
R147
10KR2J-3-GP
R150
10KR2J-3-GP
100MHz differential HTT clock
OSC_14M_NB
CPU_CLK(200MHz)
RS780M
1.1V 158R/90.9R
Title
Title
Title
CLKGEN_ICS9LPRS480
CLKGEN_ICS9LPRS480
CLKGEN_ICS9LPRS480
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
Cathedral Peak 2A
Cathedral Peak 2A
Cathedral Peak 2A
-1
-1
-1
Date:
Date:
Date:
Friday, August 22, 2008
Friday, August 22, 2008
Friday, August 22, 2008
Sheet
Sheet
Sheet
3
3
3
of
of
of
43
43
43
5
4
3
2
1
5
4
3
2
1
D
D
1D2V_S0
Place close to socket
1.5Amp
C434
C417
C416
C416
C413
C409
C409
C425
C425
C445
C445
DY
DY
DY
DY
DY
DY
DY
DY
U42A
U42A
HT LINK
HT LINK
D1
AE2
VLDT_A0
VLDT_B0
D2
AE3
VLDT_A1
VLDT_B1
D3
AE4
VLDT_A2
VLDT_B2
D4
AE5
VLDT_A3
VLDT_B3
E3
AD1
11
HT_NB_CPU_CAD_H0
L0_CADIN_H0
L0_CADOUT_H0
HT_CPU_NB_CAD_H0
11
E2
AC1
11
HT_NB_CPU_CAD_L0
L0_CADIN_L0
L0_CADOUT_L0
HT_CPU_NB_CAD_L0
11
E1
AC2
11
HT_NB_CPU_CAD_H1
L0_CADIN_H1
L0_CADOUT_H1
HT_CPU_NB_CAD_H1
11
F1
AC3
11
HT_NB_CPU_CAD_L1
L0_CADIN_L1
L0_CADOUT_L1
HT_CPU_NB_CAD_L1
11
G3
AB1
11
HT_NB_CPU_CAD_H2
L0_CADIN_H2
L0_CADOUT_H2
HT_CPU_NB_CAD_H2
11
G2
AA1
11
HT_NB_CPU_CAD_L2
HT_CPU_NB_CAD_L2
11
L0_CADIN_L2
L0_CADOUT_L2
G1
AA2
11
HT_NB_CPU_CAD_H3
HT_CPU_NB_CAD_H3
11
L0_CADIN_H3
L0_CADOUT_H3
C
C
H1
AA3
11
HT_NB_CPU_CAD_L3
HT_CPU_NB_CAD_L3
11
L0_CADIN_L3
L0_CADOUT_L3
J1
W2
11
HT_NB_CPU_CAD_H4
HT_CPU_NB_CAD_H4
11
L0_CADIN_H4
L0_CADOUT_H4
K1
W3
11
HT_NB_CPU_CAD_L4
HT_CPU_NB_CAD_L4
11
L0_CADIN_L4
L0_CADOUT_L4
L3
V1
11
HT_NB_CPU_CAD_H5
HT_CPU_NB_CAD_H5
11
L0_CADIN_H5
L0_CADOUT_H5
L2
U1
11
HT_NB_CPU_CAD_L5
HT_CPU_NB_CAD_L5
11
L0_CADIN_L5
L0_CADOUT_L5
L1
U2
11
HT_NB_CPU_CAD_H6
HT_CPU_NB_CAD_H6
11
L0_CADIN_H6
L0_CADOUT_H6
M1
U3
11
HT_NB_CPU_CAD_L6
HT_CPU_NB_CAD_L6
11
L0_CADIN_L6
L0_CADOUT_L6
N3
T1
11
HT_NB_CPU_CAD_H7
HT_CPU_NB_CAD_H7
11
L0_CADIN_H7
L0_CADOUT_H7
N2
R1
11
HT_NB_CPU_CAD_L7
L0_CADIN_L7
L0_CADOUT_L7
HT_CPU_NB_CAD_L7
11
E5
AD4
11
HT_NB_CPU_CAD_H8
L0_CADIN_H8
L0_CADOUT_H8
HT_CPU_NB_CAD_H8
11
F5
AD3
11
HT_NB_CPU_CAD_L8
L0_CADIN_L8
L0_CADOUT_L8
HT_CPU_NB_CAD_L8
11
F3
AD5
11
HT_NB_CPU_CAD_H9
L0_CADIN_H9
L0_CADOUT_H9
HT_CPU_NB_CAD_H9
11
F4
AC5
11
HT_NB_CPU_CAD_L9
L0_CADIN_L9
L0_CADOUT_L9
HT_CPU_NB_CAD_L9
11
G5
AB4
11
HT_NB_CPU_CAD_H10
L0_CADIN_H10
L0_CADOUT_H10
HT_CPU_NB_CAD_H10
11
H5
AB3
11
HT_NB_CPU_CAD_L10
L0_CADIN_L10
L0_CADOUT_L10
HT_CPU_NB_CAD_L10
11
H3
AB5
11
HT_NB_CPU_CAD_H11
L0_CADIN_H11
L0_CADOUT_H11
HT_CPU_NB_CAD_H11
11
H4
AA5
11
HT_NB_CPU_CAD_L11
L0_CADIN_L11
L0_CADOUT_L11
HT_CPU_NB_CAD_L11
11
K3
Y5
11
HT_NB_CPU_CAD_H12
L0_CADIN_H12
L0_CADOUT_H12
HT_CPU_NB_CAD_H12
11
K4
W5
11
HT_NB_CPU_CAD_L12
L0_CADIN_L12
L0_CADOUT_L12
HT_CPU_NB_CAD_L12
11
L5
V4
11
HT_NB_CPU_CAD_H13
L0_CADIN_H13
L0_CADOUT_H13
HT_CPU_NB_CAD_H13
11
M5
V3
11
HT_NB_CPU_CAD_L13
L0_CADIN_L13
L0_CADOUT_L13
HT_CPU_NB_CAD_L13
11
M3
V5
11
HT_NB_CPU_CAD_H14
L0_CADIN_H14
L0_CADOUT_H14
HT_CPU_NB_CAD_H14
11
M4
U5
11
HT_NB_CPU_CAD_L14
L0_CADIN_L14
L0_CADOUT_L14
HT_CPU_NB_CAD_L14
11
N5
T4
11
HT_NB_CPU_CAD_H15
HT_CPU_NB_CAD_H15
11
L0_CADIN_H15
L0_CADOUT_H15
P5
T3
11
HT_NB_CPU_CAD_L15
HT_CPU_NB_CAD_L15
11
L0_CADIN_L15
L0_CADOUT_L15
J3
Y1
11
HT_NB_CPU_CLK_H0
HT_CPU_NB_CLK_H0
11
L0_CLKIN_H0
L0_CLKOUT_H0
J2
W1
11
HT_NB_CPU_CLK_L0
HT_CPU_NB_CLK_L0
11
L0_CLKIN_L0
L0_CLKOUT_L0
J5
Y4
11
HT_NB_CPU_CLK_H1
HT_CPU_NB_CLK_H1
11
L0_CLKIN_H1
L0_CLKOUT_H1
B
B
K5
Y3
11
HT_NB_CPU_CLK_L1
HT_CPU_NB_CLK_L1
11
L0_CLKIN_L1
L0_CLKOUT_L1
N1
R2
11
HT_NB_CPU_CTL_H0
HT_CPU_NB_CTL_H0
11
L0_CTLIN_H0
L0_CTLOUT_H0
P1
R3
11
HT_NB_CPU_CTL_L0
HT_CPU_NB_CTL_L0
11
L0_CTLIN_L0
L0_CTLOUT_L0
P3
T5
11
HT_NB_CPU_CTL_H1
L0_CTLIN_H1
L0_CTLOUT_H1
HT_CPU_NB_CTL_H1
11
P4
R5
11
HT_NB_CPU_CTL_L1
L0_CTLIN_L1
L0_CTLOUT_L1
HT_CPU_NB_CTL_L1
11
SKT-CPU638P-GP-U2
62.10055.111
2ND = 62.10055.251
SKT-CPU638P-GP-U2
62.10055.111
2ND = 62.10055.251
SKT-BGA638H176
<Core Design>
<Core Design>
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_HT_LINK I/F_(1/4)
CPU_HT_LINK I/F_(1/4)
CPU_HT_LINK I/F_(1/4)
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
Cathedral Peak 2A
Cathedral Peak 2A
Cathedral Peak 2A
-1
-1
-1
Date:
Date:
Date:
Friday, August 22, 2008
Friday, August 22, 2008
Friday, August 22, 2008
Sheet
Sheet
Sheet
4
4
4
of
of
of
43
43
43
5
4
3
2
1
5
4
3
2
1
U42C
U42C
MEM:DATA
MEM:DATA
G12
C11
8
MEM_MA_DATA0
MA_DATA0
MB_DATA0
MEM_MB_DATA0 9
F12
A11
8
MEM_MA_DATA1
MA_DATA1
MB_DATA1
MEM_MB_DATA1 9
H14
A14
8
MEM_MA_DATA2
MA_DATA2
MB_DATA2
MEM_MB_DATA2 9
G14
B14
8
MEM_MA_DATA3
MA_DATA3
MB_DATA3
MEM_MB_DATA3 9
H11
G11
8
MEM_MA_DATA4
MA_DATA4
MB_DATA4
MEM_MB_DATA4 9
H12
E11
8
MEM_MA_DATA5
MA_DATA5
MB_DATA5
MEM_MB_DATA5 9
C13
D12
8
MEM_MA_DATA6
MA_DATA6
MB_DATA6
MEM_MB_DATA6 9
E13
A13
8
MEM_MA_DATA7
MA_DATA7
MB_DATA7
MEM_MB_DATA7 9
Place near to CPU
H15
A15
8
MEM_MA_DATA8
MA_DATA8
MB_DATA8
MEM_MB_DATA8 9
E15
A16
8
MEM_MA_DATA9
MA_DATA9
MB_DATA9
MEM_MB_DATA9 9
4.7u x 4
0.22u X 2
180P x 6
E17
A19
D
D
8
MEM_MA_DATA10
MA_DATA10
MB_DATA10
MEM_MB_DATA10 9
H17
A20
8
MEM_MA_DATA11
MA_DATA11
MB_DATA11
MEM_MB_DATA11 9
E14
C14
8
MEM_MA_DATA12
MEM_MB_DATA12 9
MA_DATA12
MB_DATA12
C175
C175
C169
C169
C165
C154
C156
C156
C155
C155
C160
C150
C157
C153
C161
C158
C158
F14
D14
8
MEM_MA_DATA13
MEM_MB_DATA13 9
MA_DATA13
MB_DATA13
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
C17
C18
8
MEM_MA_DATA14
MEM_MB_DATA14 9
MA_DATA14
MB_DATA14
G17
D18
8
MEM_MA_DATA15
MEM_MB_DATA15 9
MA_DATA15
MB_DATA15
G18
D20
8
MEM_MA_DATA16
MEM_MB_DATA16 9
MA_DATA16
MB_DATA16
C19
A21
8
MEM_MA_DATA17
MEM_MB_DATA17 9
MA_DATA17
MB_DATA17
D22
D24
8
MEM_MA_DATA18
MEM_MB_DATA18 9
MA_DATA18
MB_DATA18
E20
C25
8
MEM_MA_DATA19
MEM_MB_DATA19 9
MA_DATA19
MB_DATA19
E18
B20
8
MEM_MA_DATA20
MEM_MB_DATA20 9
MA_DATA20
MB_DATA20
F18
C20
8
MEM_MA_DATA21
MEM_MB_DATA21 9
MA_DATA21
MB_DATA21
B22
B24
8
MEM_MA_DATA22
MA_DATA22
MB_DATA22
MEM_MB_DATA22 9
C23
C24
8
MEM_MA_DATA23
MA_DATA23
MB_DATA23
MEM_MB_DATA23 9
F20
E23
8
MEM_MA_DATA24
MA_DATA24
MB_DATA24
MEM_MB_DATA24 9
F22
E24
8
MEM_MA_DATA25
MA_DATA25
MB_DATA25
MEM_MB_DATA25 9
H24
G25
8
MEM_MA_DATA26
MA_DATA26
MB_DATA26
MEM_MB_DATA26 9
J19
G26
8
MEM_MA_DATA27
MA_DATA27
MB_DATA27
MEM_MB_DATA27 9
E21
C26
0D9V_S3
8
MEM_MA_DATA28
MA_DATA28
MB_DATA28
MEM_MB_DATA28 9
750 mA
E22
D26
8
MEM_MA_DATA29
MA_DATA29
MB_DATA29
MEM_MB_DATA29 9
CLOSE TO CPU
H20
G23
8
MEM_MA_DATA30
MA_DATA30
MB_DATA30
MEM_MB_DATA30 9
H22
G24
8
MEM_MA_DATA31
MA_DATA31
MB_DATA31
MEM_MB_DATA31 9
Y24
AA24
1D8V_S3
8
MEM_MA_DATA32
MA_DATA32
MB_DATA32
MEM_MB_DATA32 9
U42B
U42B
AB24
AA23
8
MEM_MA_DATA33
MA_DATA33
MB_DATA33
MEM_MB_DATA33 9
AB22
AD24
8
MEM_MA_DATA34
MA_DATA34
MB_DATA34
MEM_MB_DATA34 9
D10
W10
AA21
AE24
VTT1
VTT5
8
MEM_MA_DATA35
MA_DATA35
MB_DATA35
MEM_MB_DATA35 9
C10
MEM:CMD/CTRL/CLK
MEM:CMD/CTRL/CLK
AC10
W22
AA26
VTT2
VTT6
8
MEM_MA_DATA36
MA_DATA36
MB_DATA36
MEM_MB_DATA36 9
B10
AB10
C189
SCD1U10V2KX-4GP
W21
AA25
8
MEM_MA_DATA37
MEM_MB_DATA37 9
VTT3
VTT7
MA_DATA37
MB_DATA37
R273
39D2R2F-L-GP
AD10
AA10
Y22
AD26
8
MEM_MA_DATA38
MEM_MB_DATA38 9
VTT4
VTT8
MA_DATA38
MB_DATA38
1D8V_S3
C
C
A10
AA22
AE25
8
MEM_MA_DATA39
MEM_MB_DATA39 9
VTT9
MA_DATA39
MB_DATA39
MEMZP
MEMZN
MEM_RSVD_M1
1
2
AF10
Y20
AC22
8
MEM_MA_DATA40
MEM_MB_DATA40 9
MEMZP
VREF_DDR_CLAW
MA_DATA40
MB_DATA40
VTT_SENSE
RN21
RN21
1
2
AE10
Y10
1
TP83 TPAD14-GP
TP83 TPAD14-GP
AA20
AD22
8
MEM_MA_DATA41
MEM_MB_DATA41 9
MEMZN
VTT_SENSE
MA_DATA41
MB_DATA41
R263
39D2R2F-L-GP
1
2
4
AA18
AE20
8
MEM_MA_DATA42
MEM_MB_DATA42 9
MA_DATA42
MB_DATA42
TP119
TP119
1
H16
W17
3
AB18
AF20
8
MEM_MA_DATA43
MEM_MB_DATA43 9
RSVD_M1
MEMVREF
MA_DATA43
MB_DATA43
AB21
AF24
8
MEM_MA_DATA44
MEM_MB_DATA44 9
MA_DATA44
MB_DATA44
MEM_RSVD_M2
TP120
TP120
C186
C183
SRN1KJ-7-GP
SRN1KJ-7-GP
T19
B18
1
AD21
AF23
8,10
MEM_MA0_ODT0
8
MEM_MA_DATA45
MEM_MB_DATA45 9
MA0_ODT0
RSVD_M2
MA_DATA45
MB_DATA45
V22
AD19
AC20
8,10
MEM_MA0_ODT1
8
MEM_MA_DATA46
MEM_MB_DATA46 9
MA0_ODT1
MA_DATA46
MB_DATA46
U21
W26
Y18
AD20
MA1_ODT0
MB0_ODT0
MEM_MB0_ODT0 9,10
8
MEM_MA_DATA47
MA_DATA47
MB_DATA47
MEM_MB_DATA47 9
V19
W23
AD17
AD18
MA1_ODT1
MB0_ODT1
MEM_MB0_ODT1 9,10
8
MEM_MA_DATA48
MA_DATA48
MB_DATA48
MEM_MB_DATA48 9
Y26
W16
AE18
MB1_ODT0
8
MEM_MA_DATA49
MA_DATA49
MB_DATA49
MEM_MB_DATA49 9
T20
W14
AC14
8,10
MEM_MA0_CS#0
MA0_CS_L0
8
MEM_MA_DATA50
MA_DATA50
MB_DATA50
MEM_MB_DATA50 9
U19
V26
Y14
AD14
8,10
MEM_MA0_CS#1
MA0_CS_L1
MB0_CS_L0
MEM_MB0_CS#0 9,10
MEM_MB0_CS#1 9,10
8
MEM_MA_DATA51
MA_DATA51
MB_DATA51
MEM_MB_DATA51 9
U20
W25
Y17
AF19
MA1_CS_L0
MB0_CS_L1
8
MEM_MA_DATA52
MA_DATA52
MB_DATA52
MEM_MB_DATA52 9
V20
U22
AB17
AC18
MA1_CS_L1
MB1_CS_L0
8
MEM_MA_DATA53
MA_DATA53
MB_DATA53
MEM_MB_DATA53 9
AB15
AF16
8
MEM_MA_DATA54
MA_DATA54
MB_DATA54
MEM_MB_DATA54 9
J22
J25
AD15
AF15
8,10
MEM_MA_CKE0
MA_CKE0
MB_CKE0
MEM_MB_CKE0 9,10
MEM_MB_CKE1 9,10
8
MEM_MA_DATA55
MA_DATA55
MB_DATA55
MEM_MB_DATA55 9
J20
H26
AB13
AF13
8,10
MEM_MA_CKE1
MA_CKE1
MB_CKE1
8
MEM_MA_DATA56
MA_DATA56
MB_DATA56
MEM_MB_DATA56 9
AD13
AC12
8
MEM_MA_DATA57
MA_DATA57
MB_DATA57
MEM_MB_DATA57 9
N19
P22
Y12
AB11
MA_CLK_H5
MB_CLK_H5
8
MEM_MA_DATA58
MA_DATA58
MB_DATA58
MEM_MB_DATA58 9
N20
R22
W11
Y11
MA_CLK_L5
MB_CLK_L5
8
MEM_MA_DATA59
MA_DATA59
MB_DATA59
MEM_MB_DATA59 9
E16
A17
AB14
AE14
8
MEM_MA_CLK0_P
MA_CLK_H1
MB_CLK_H1
MEM_MB_CLK0_P 9
8
MEM_MA_DATA60
MA_DATA60
MB_DATA60
MEM_MB_DATA60 9
F16
A18
AA14
AF14
8
MEM_MA_CLK0_N
MA_CLK_L1
MB_CLK_L1
MEM_MB_CLK0_N
9
8
MEM_MA_DATA61
MA_DATA61
MB_DATA61
MEM_MB_DATA61 9
Y16
AF18
AB12
AF11
8
MEM_MA_CLK1_P
MEM_MB_CLK1_P 9
MEM_MB_CLK1_N
8
MEM_MA_DATA62
MEM_MB_DATA62 9
MA_CLK_H7
MB_CLK_H7
MA_DATA62
MB_DATA62
AA16
AF17
AA12
AD11
8
MEM_MA_CLK1_N
9
8
MEM_MA_DATA63
MEM_MB_DATA63 9
MA_CLK_L7
MB_CLK_L7
MA_DATA63
MB_DA
T
A63
P19
R26
MA_CLK_H4
MB_CLK_H4
P20
R25
E12
A12
8
MEM_MA_DM0
MEM_MB_DM0 9
MA_CLK_L4
MB_CLK_L4
MA_DM0
MB_DM0
C15
B16
8
MEM_MA_DM1
MEM_MB_DM1 9
MA_DM1
MB_DM1
N21
P24
E19
A22
8,10
MEM_MA_ADD0
MEM_MB_ADD0
9,10
8
MEM_MA_DM2
MEM_MB_DM2 9
MA_ADD0
MB_ADD0
MA_DM2
MB_DM2
B
B
M20
N24
F24
E25
8,10
MEM_MA_ADD1
MEM_MB_ADD1
9,10
8
MEM_MA_DM3
MEM_MB_DM3 9
MA_ADD1
MB_ADD1
MA_DM3
MB_DM3
N22
P26
AC24
AB26
8,10
MEM_MA_ADD2
MEM_MB_ADD2
9,10
8
MEM_MA_DM4
MEM_MB_DM4 9
MA_ADD2
MB_ADD2
MA_DM4
MB_DM4
M19
N23
Y19
AE22
8,10
MEM_MA_ADD3
MEM_MB_ADD3
9,10
8
MEM_MA_DM5
MEM_MB_DM5 9
MA_ADD3
MB_ADD3
MA_DM5
MB_DM5
M22
N26
AB16
AC16
8,10
MEM_MA_ADD4
MEM_MB_ADD4
9,10
8
MEM_MA_DM6
MEM_MB_DM6 9
MA_ADD4
MB_ADD4
MA_DM6
MB_DM6
L20
L23
Y13
AD12
8,10
MEM_MA_ADD5
MA_ADD5
MB_ADD5
MEM_MB_ADD5
9,10
8
MEM_MA_DM7
MA_DM7
MB_DM7
MEM_MB_DM7 9
M24
N25
8,10
MEM_MA_ADD6
MA_ADD6
MB_ADD6
MEM_MB_ADD6
9,10
L21
L24
G13
C12
8,10
MEM_MA_ADD7
MA_ADD7
MB_ADD7
MEM_MB_ADD7
9,10
8
MEM_MA_DQS0_P
MA_DQS_H0
MB_DQS_H0
MEM_MB_DQS0_P 9
MEM_MB_DQS0_N
L19
M26
H13
B12
8,10
MEM_MA_ADD8
MA_ADD8
MB_ADD8
MEM_MB_ADD8
9,10
8
MEM_MA_DQS0_N
MA_DQS_L0
MB_DQS_L0
9
K22
K26
G16
D16
8,10
MEM_MA_ADD9
MA_ADD9
MB_ADD9
MEM_MB_ADD9
9,10
8
MEM_MA_DQS1_P
MA_DQS_H1
MB_DQS_H1
MEM_MB_DQS1_P 9
MEM_MB_DQS1_N
R21
T26
G15
C16
8,10
MEM_MA_ADD10
MA_ADD10
MB_ADD10
MEM_MB_ADD10
9,10
8
MEM_MA_DQS1_N
MA_DQS_L1
MB_DQS_L1
9
L22
L26
C22
A24
8,10
MEM_MA_ADD11
MA_ADD11
MB_ADD11
MEM_MB_ADD11
9,10
8
MEM_MA_DQS2_P
MA_DQS_H2
MB_DQS_H2
MEM_MB_DQS2_P 9
MEM_MB_DQS2_N
K20
L25
C21
A23
8,10
MEM_MA_ADD12
MA_ADD12
MB_ADD12
MEM_MB_ADD12
9,10
8
MEM_MA_DQS2_N
MA_DQS_L2
MB_DQS_L2
9
V24
W24
G22
F26
8,10
MEM_MA_ADD13
MA_ADD13
MB_ADD13
MEM_MB_ADD13
9,10
8
MEM_MA_DQS3_P
MA_DQS_H3
MB_DQS_H3
MEM_MB_DQS3_P 9
K24
J23
G21
E26
8,10
MEM_MA_ADD14
MA_ADD14
MB_ADD14
MEM_MB_ADD14
9,10
8
MEM_MA_DQS3_N
MA_DQS_L3
MB_DQS_L3
MEM_MB_DQS3_N
9
K19
J24
AD23
AC25
8,10
MEM_MA_ADD15
MA_ADD15
MB_ADD15
MEM_MB_ADD15
9,10
8
MEM_MA_DQS4_P
MA_DQS_H4
MB_DQS_H4
MEM_MB_DQS4_P 9
MEM_MB_DQS4_N
AC23
AC26
8
MEM_MA_DQS4_N
MA_DQS_L4
MB_DQS_L4
9
R20
R24
AB19
AF21
8,10
MEM_MA_BANK0
MA_BANK0
MB_BANK0
MEM_MB_BANK0 9,10
MEM_MB_BANK1 9,10
MEM_MB_BANK2 9,10
MEM_MB_RAS# 9,10
MEM_MB_CAS# 9,10
MEM_MB_WE# 9,10
8
MEM_MA_DQS5_P
MA_DQS_H5
MB_DQS_H5
MEM_MB_DQS5_P 9
MEM_MB_DQS5_N
R23
U26
AB20
AF22
8,10
MEM_MA_BANK1
MA_BANK1
MB_BANK1
8
MEM_MA_DQS5_N
MA_DQS_L5
MB_DQS_L5
9
J21
J26
Y15
AE16
8,10
MEM_MA_BANK2
MA_BANK2
MB_BANK2
8
MEM_MA_DQS6_P
MA_DQS_H6
MB_DQS_H6
MEM_MB_DQS6_P 9
MEM_MB_DQS6_N
W15
AD16
8
MEM_MA_DQS6_N
9
MA_DQS_L6
MB_DQS_L6
R19
U25
W12
AF12
8,10
MEM_MA_RAS#
8
MEM_MA_DQS7_P
MEM_MB_DQS7_P 9
MEM_MB_DQS7_N
MA_RAS_L
MB_RAS_L
MA_DQS_H7
MB_DQS_H7
T22
U24
W13
AE12
8,10
MEM_MA_CAS#
8
MEM_MA_DQS7_N
9
MA_CAS_L
MB_CAS_L
MA_DQS_L7
MB_DQS_L7
T24
U23
8,10
MEM_MA_WE#
MA_WE_L
MB_WE_L
SKT-CPU638P-GP-U2
SKT-CPU638P-GP-U2
SKT-CPU638P-GP-U2
SKT-CPU638P-GP-U2
<Core Design>
<Core Design>
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_DDR_(2/4)
CPU_DDR_(2/4)
CPU_DDR_(2/4)
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
Cathedral Peak 2A
Cathedral Peak 2A
Cathedral Peak 2A
-1
-1
-1
Date:
Date:
Date:
Friday, August 22, 2008
Friday, August 22, 2008
Friday, August 22, 2008
Sheet
Sheet
Sheet
5
5
5
of
of
of
43
43
43
5
4
3
2
1
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